Patents by Inventor Kan Murata
Kan Murata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10360029Abstract: Provided is a signal processing circuit occupying a small circuit area. A common arithmetic operation element is shared between a plurality of arithmetic operation sequence control units. An arbitration circuit selects, when the plurality of arithmetic operation sequence control units simultaneously generate requests for arithmetic operations to use the common arithmetic operation element, the predetermined sequence control unit based on priority information about the plurality of arithmetic operation sequence control units, causes the common arithmetic operation element to execute the arithmetic operation requested from the selected arithmetic operation sequence control unit, and returns the result of the arithmetic operation to the selected arithmetic operation sequence control unit.Type: GrantFiled: April 2, 2018Date of Patent: July 23, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hiroyuki Yamasaki, Hideyuki Noda, Kan Murata
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Publication number: 20180225115Abstract: Provided is a signal processing circuit occupying a small circuit area. A common arithmetic operation element is shared between a plurality of arithmetic operation sequence control units. An arbitration circuit selects, when the plurality of arithmetic operation sequence control units simultaneously generate requests for arithmetic operations to use the common arithmetic operation element, the predetermined sequence control unit based on priority information about the plurality of arithmetic operation sequence control units, causes the common arithmetic operation element to execute the arithmetic operation requested from the selected arithmetic operation sequence control unit, and returns the result of the arithmetic operation to the selected arithmetic operation sequence control unit.Type: ApplicationFiled: April 2, 2018Publication date: August 9, 2018Inventors: Hiroyuki YAMASAKI, Hideyuki NODA, Kan MURATA
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Patent number: 9965273Abstract: Provided is a signal processing circuit occupying a small circuit area. A common arithmetic operation element is shared between a plurality of arithmetic operation sequence control units. An arbitration circuit selects, when the plurality of arithmetic operation sequence control units simultaneously generate requests for arithmetic operations to use the common arithmetic operation element, the predetermined sequence control unit based on priority information about the plurality of arithmetic operation sequence control units, causes the common arithmetic operation element to execute the arithmetic operation requested from the selected arithmetic operation sequence control unit, and returns the result of the arithmetic operation to the selected arithmetic operation sequence control unit.Type: GrantFiled: November 23, 2016Date of Patent: May 8, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hiroyuki Yamasaki, Hideyuki Noda, Kan Murata
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Publication number: 20170075687Abstract: Provided is a signal processing circuit occupying a small circuit area. A common arithmetic operation element is shared between a plurality of arithmetic operation sequence control units. An arbitration circuit selects, when the plurality of arithmetic operation sequence control units simultaneously generate requests for arithmetic operations to use the common arithmetic operation element, the predetermined sequence control unit based on priority information about the plurality of arithmetic operation sequence control units, causes the common arithmetic operation element to execute the arithmetic operation requested from the selected arithmetic operation sequence control unit, and returns the result of the arithmetic operation to the selected arithmetic operation sequence control unit.Type: ApplicationFiled: November 23, 2016Publication date: March 16, 2017Inventors: Hiroyuki YAMASAKI, Hideyuki NODA, Kan MURATA
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Patent number: 9558151Abstract: Disclosed is a data processing device capable of efficiently performing an arithmetic process on variable-length data and an arithmetic process on fixed-length data. The data processing device includes first PEs of SIMD type, SRAMs provided respectively for the first PEs, and second PEs. The first PEs each perform an arithmetic operation on data stored in a corresponding one of the SRAMs. The second PEs each perform an arithmetic operation on data stored in corresponding ones of the SRAMs. Therefore, the SRAMs can be shared so as to efficiently perform the arithmetic process on variable-length data and the arithmetic process on fixed-length data.Type: GrantFiled: February 3, 2012Date of Patent: January 31, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kan Murata, Hideyuki Noda, Masaru Haraguchi
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Patent number: 9535693Abstract: Provided is a signal processing circuit occupying a small circuit area. A common arithmetic operation element is shared between a plurality of arithmetic operation sequence control units. An arbitration circuit selects, when the plurality of arithmetic operation sequence control units simultaneously generate requests for arithmetic operations to use the common arithmetic operation element, the predetermined sequence control unit based on priority information about the plurality of arithmetic operation sequence control units, causes the common arithmetic operation element to execute the arithmetic operation requested from the selected arithmetic operation sequence control unit, and returns the result of the arithmetic operation to the selected arithmetic operation sequence control unit.Type: GrantFiled: April 17, 2013Date of Patent: January 3, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hiroyuki Yamasaki, Hideyuki Noda, Kan Murata
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Patent number: 8612981Abstract: A method for distributing a task to plural processors is provided. A distribution rule of distributing plural tasks to sub processors or the main processor, respectively, is previously written in a program code of an application configured to include plural tasks. At the time of executing the application, the main processor reads out the distribution rule, and distributes plural tasks to the sub processors or the main processor, respectively, in accordance with the distribution rule.Type: GrantFiled: September 13, 2007Date of Patent: December 17, 2013Assignees: Sony Corporation, Sony Computer Entertainment Inc.Inventor: Kan Murata
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Publication number: 20130283016Abstract: Provided is a signal processing circuit occupying a small circuit area. A common arithmetic operation element is shared between a plurality of arithmetic operation sequence control units. An arbitration circuit selects, when the plurality of arithmetic operation sequence control units simultaneously generate requests for arithmetic operations to use the common arithmetic operation element, the predetermined sequence control unit based on priority information about the plurality of arithmetic operation sequence control units, causes the common arithmetic operation element to execute the arithmetic operation requested from the selected arithmetic operation sequence control unit, and returns the result of the arithmetic operation to the selected arithmetic operation sequence control unit.Type: ApplicationFiled: April 17, 2013Publication date: October 24, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Hiroyuki YAMASAKI, Hideyuki NODA, Kan MURATA
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Publication number: 20120265964Abstract: Disclosed is a data processing device capable of efficiently performing an arithmetic process on variable-length data and an arithmetic process on fixed-length data. The data processing device includes first PEs of SIMD type, SRAMs provided respectively for the first PEs, and second PEs. The first PEs each perform an arithmetic operation on data stored in a corresponding one of the SRAMs. The second PEs each perform an arithmetic operation on data stored in corresponding ones of the SRAMs. Therefore, the SRAMs can be shared so as to efficiently perform the arithmetic process on variable-length data and the arithmetic process on fixed-length data.Type: ApplicationFiled: February 3, 2012Publication date: October 18, 2012Inventors: Kan MURATA, Hideyuki Noda, Masaru Haraguchi
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Publication number: 20080109815Abstract: A method for distributing a task to plural processors is provided. A distribution rule of distributing plural tasks to sub processors or the main processor, respectively, is previously written in a program code of an application configured to include plural tasks. At the time of executing the application, the main processor reads out the distribution rule, and distributes plural tasks to the sub processors or the main processor, respectively, in accordance with the distribution rule.Type: ApplicationFiled: September 13, 2007Publication date: May 8, 2008Applicant: SONY COMPUTER ENTERTAINMENT INC.Inventor: Kan Murata