Abstract: A semiconductor device with a reduced tail current is provided. The semiconductor device includes a first junction field effect transistor. The first junction field effect transistor includes a drift layer of a first conductivity type, a first source region of the first conductivity type, a first gate region of a second conductivity type, a first drain region of the first conductivity type, a semiconductor region of the second conductivity type, and a control electrode. The first source region is provided in the semiconductor region. The control electrode is electrically connected to the semiconductor region.

Abstract: A semiconductor device includes a semiconductor substrate, an insulating layer, a transformer formed in the insulating layer, and a wiring. The transformer includes a primary winding conductor, and a secondary winding conductor. The primary winding conductor is provided in a quadrangle spiral shape having a first center axis extending in a direction parallel to the surface of the semiconductor substrate inside the insulating layer, and configured by one conductor film selected from a group consisting of a vacuum deposition film, a chemical vapor deposition film and a sputtered film. The secondary winding conductor is provided in a quadrangle spiral shape having a second center axis inside the insulating layer while being spaced from the primary winding conductor in plan view of the semiconductor substrate, magnetically coupled with the primary winding conductor and configured by a conductor film.

Abstract: A semiconductor device with a reduced tail current is provided. The semiconductor device includes a first junction field effect transistor. The first junction field effect transistor includes a drift layer of a first conductivity type, a first source region of the first conductivity type, a first gate region of a second conductivity type, a first drain region of the first conductivity type, a semiconductor region of the second conductivity type, and a control electrode. The first source region is provided in the semiconductor region. The control electrode is electrically connected to the semiconductor region.

Abstract: A semiconductor device includes a P-type low potential region, an N-type first region, an N-type second region, an N-type third region, an annular trench, and a P-type isolation region. The N-type first region is provided on the principal surface of a P-type SOI layer provided to a P-type SOI substrate. The N-type first region has a concave portion. The N-type third region is provided inside the concave portion of the N-type first region so as to be away from the edge of the concave portion. A level-shift device is formed on the surface of the N-type third region. The P-type isolation region is a slit region extending in U-shape along the boundary between the N-type third region and the concave portion of the N-type first region.

Abstract: A semiconductor device includes a semiconductor substrate, an insulating layer, a transformer formed in the insulating layer, and a wiring. The transformer includes a primary winding conductor, and a secondary winding conductor. The primary winding conductor is provided in a quadrangle spiral shape having a first center axis extending in a direction parallel to the surface of the semiconductor substrate inside the insulating layer, and configured by one conductor film selected from a group consisting of a vacuum deposition film, a chemical vapor deposition film and a sputtered film. The secondary winding conductor is provided in a quadrangle spiral shape having a second center axis inside the insulating layer while being spaced from the primary winding conductor in plan view of the semiconductor substrate, magnetically coupled with the primary winding conductor and configured by a conductor film.

Abstract: A semiconductor device includes a P-type low potential region, an N-type first region, an N-type second region, an N-type third region, an annular trench, and a P-type isolation region. The N-type first region is provided on the principal surface of a P-type SOI layer provided to a P-type SOI substrate. The N-type first region has a concave portion. The N-type third region is provided inside the concave portion of the N-type first region so as to be away from the edge of the concave portion. A level-shift device is formed on the surface of the N-type third region. The P-type isolation region is a slit region extending in U-shape along the boundary between the N-type third region and the concave portion of the N-type first region.