Patents by Inventor Kan Yasui
Kan Yasui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230420555Abstract: Provided is a semiconductor device where an electric field applied to an electric field protection layer at a bottom of a trench gate electrode of an active region is relaxed and an avalanche withstand voltage is improved. The semiconductor device includes: an active region that has multiple gate trenches, a trench gate electrode in each gate trench, and a P body layer provided to a section other than the gate trenches; and a termination region disposed on the outer periphery of the active region. Additionally, an electric field protection layer is provided to the bottom of each gate trench of the active region, an electric field relaxation layer is between the active region and the termination region, the bottom surface of the electric field relaxation layer is shallower than that of the electric field protection layer, and the electric field relaxation layer is electrically connected to the P body layer.Type: ApplicationFiled: November 18, 2021Publication date: December 28, 2023Applicant: HITACHI POWER SEMICONDUCTOR DEVICE, LTD.Inventors: Koyo KINOSHITA, Takahiro MORIKAWA, Tatsunori MURATA, Kan YASUI
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Patent number: 10910394Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: GrantFiled: May 22, 2020Date of Patent: February 2, 2021Assignee: Renesas Electronics CorporationInventors: Tsutomu Okazaki, Akira Kato, Kan Yasui, Kyoya Nitta, Digh Hisamoto, Yasushi Ishii, Daisuke Okada, Toshihiro Tanaka, Toshikazu Matsui
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Publication number: 20200357807Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: ApplicationFiled: May 22, 2020Publication date: November 12, 2020Inventors: Tsutomu OKAZAKI, Akira KATO, Kan YASUI, Kyoya NITTA, Digh HISAMOTO, Yasushi ISHII, Daisuke OKADA, Toshihiro TANAKA, Toshikazu MATSUI
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Patent number: 10692878Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: GrantFiled: August 27, 2019Date of Patent: June 23, 2020Assignee: Renesas Electronics CorporationInventors: Tsutomu Okazaki, Akira Kato, Kan Yasui, Kyoya Nitta, Digh Hisamoto, Yasushi Ishii, Daisuke Okada, Toshihiro Tanaka, Toshikazu Matsui
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Patent number: 10522638Abstract: A semiconductor chip includes a semiconductor substrate made of SiC, a front surface electrode formed in a principal surface of the semiconductor substrate, and a rear surface electrode (drain electrode) formed in a rear surface of the semiconductor substrate. The front surface electrode is bonded to a wire, and includes an Al alloy film containing a high melting-point metal. The Al alloy film contains a columnar Al crystal which extends along a thickness direction of the Al alloy film, and an intermetallic compound is precipitated therein.Type: GrantFiled: October 5, 2018Date of Patent: December 31, 2019Assignee: HITACHI POWER SEMICONDUCTOR DEVICE, LTD.Inventors: Masakazu Sagawa, Takahiro Morikawa, Motoyuki Miyata, Kan Yasui, Toshiaki Morita
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Publication number: 20190386013Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: ApplicationFiled: August 27, 2019Publication date: December 19, 2019Inventors: Tsutomu OKAZAKI, Akira KATO, Kan YASUI, Kyoya NITTA, Digh HISAMOTO, Yasushi ISHII, Daisuke OKADA, Toshihiro TANAKA, Toshikazu MATSUI
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Patent number: 10396089Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: GrantFiled: November 27, 2018Date of Patent: August 27, 2019Assignee: Renesas Electronics CorporationInventors: Tsutomu Okazaki, Daisuke Okada, Kyoya Nitta, Toshihiro Tanaka, Akira Kato, Toshikazu Matsui, Yasushi Ishii, Digh Hisamoto, Kan Yasui
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Publication number: 20190157412Abstract: A semiconductor chip includes a semiconductor substrate made of SiC, a front surface electrode formed in a principal surface of the semiconductor substrate, and a rear surface electrode (drain electrode) formed in a rear surface of the semiconductor substrate. The front surface electrode is bonded to a wire, and includes an Al alloy film containing a high melting-point metal. The Al alloy film contains a columnar Al crystal which extends along a thickness direction of the Al alloy film, and an intermetallic compound is precipitated therein.Type: ApplicationFiled: October 5, 2018Publication date: May 23, 2019Inventors: Masakazu SAGAWA, Takahiro MORIKAWA, Motoyuki MIYATA, Kan YASUI, Toshiaki MORITA
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Publication number: 20190096896Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: ApplicationFiled: November 27, 2018Publication date: March 28, 2019Inventors: Tsutomu OKAZAKI, Daisuke OKADA, Kyoya NITTA, Toshihiro TANAKA, Akira KATO, Toshikazu MATSUI, Yasushi ISHII, Digh HISAMOTO, Kan YASUI
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Patent number: 10141324Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: GrantFiled: April 28, 2017Date of Patent: November 27, 2018Assignee: Renesas Electronics CorporationInventors: Tsutomu Okazaki, Daisuke Okada, Kyoya Nitta, Toshihiro Tanaka, Akira Kato, Toshikazu Matsui, Yasushi Ishii, Digh Hisamoto, Kan Yasui
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Patent number: 10109549Abstract: In order to improve productivity of a semiconductor device, while improving stability of the blocking voltage of the semiconductor device, this semiconductor device is characterized by having a semiconductor element, and a laminated structure having three resin layers, said laminated structure being in a peripheral section surrounding a main electrode on one surface of the semiconductor element. The semiconductor device is also characterized in that the laminated structure has, on the center section side of the semiconductor element, a region where a lower resin layer is in contact with an intermediate resin layer, and a region where the lower resin layer is in contact with an upper resin layer.Type: GrantFiled: December 24, 2014Date of Patent: October 23, 2018Assignee: Hitachi, Ltd.Inventors: Takashi Hirao, Kan Yasui, Kazuhiro Suzuki
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Patent number: 10083948Abstract: In order to form, in a wide band gap semiconductor device, a high field resistant sealing material having a large end portion film thickness, said high field resistant sealing material corresponding to a reduced termination region having a high field intensity, and to improve accuracy and shorten time of manufacturing steps, this semiconductor device is configured as follows. At least a part of a cross-section of a high field resistant sealing material formed close to a termination region at the periphery of a semiconductor chip has a perpendicular shape at a chip outer peripheral end portion, said shape having, on the chip inner end side, a film thickness that is reduced toward the inner side. In a semiconductor device manufacturing method for providing such semiconductor device, the high field resistant sealing material is formed in a semiconductor wafer state, then, heat treatment is performed, and after dicing is performed, a chip is mounted.Type: GrantFiled: December 26, 2014Date of Patent: September 25, 2018Assignee: Hitachi, Ltd.Inventors: Kan Yasui, Kazuhiro Suzuki, Takafumi Taniguchi
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Publication number: 20180047855Abstract: In a Schottky barrier diode comprising silicon carbide: an active region includes a first semiconductor region of a first conductivity type configuring a first Schottky junction having a plurality of linear patterns between a first electrode and the first semiconductor region and a second semiconductor region of a second conductivity type adjacent to the first Schottky junction and connected to the first electrode; at the border of the active region and a periphery region, a second Schottky junction comprising the first electrode and the first semiconductor region and having at least one annular pattern surrounding the linear patterns is provided and the second semiconductor region is adjacent to the second Schottky junction and is connected to the first electrode; and the first and second Schottky junctions are conductive parts and the second semiconductor region is a nonconductive part in a forward bias state.Type: ApplicationFiled: May 15, 2015Publication date: February 15, 2018Inventors: Kan YASUI, Hiroyuki MATSUSHIMA, Hiroyuki OKINO
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Publication number: 20170352604Abstract: In order to improve productivity of a semiconductor device, while improving stability of the blocking voltage of the semiconductor device, this semiconductor device is characterized by having a semiconductor element, and a laminated structure having three resin layers, said laminated structure being in a peripheral section surrounding a main electrode on one surface of the semiconductor element. The semiconductor device is also characterized in that the laminated structure has, on the center section side of the semiconductor element, a region where a lower resin layer is in contact with an intermediate resin layer, and a region where the lower resin layer is in contact with an upper resin layer.Type: ApplicationFiled: December 24, 2014Publication date: December 7, 2017Applicant: Hitachi, Ltd.Inventors: Takashi HIRAO, Kan YASUI, Kazuhiro SUZUKI
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Publication number: 20170352648Abstract: In order to form, in a wide band gap semiconductor device, a high field resistant sealing material having a large end portion film thickness, said high field resistant sealing material corresponding to a reduced termination region having a high field intensity, and to improve accuracy and shorten time of manufacturing steps, this semiconductor device is configured as follows. At least a part of a cross-section of a high field resistant sealing material formed close to a termination region at the periphery of a semiconductor chip has a perpendicular shape at a chip outer peripheral end portion, said shape having, on the chip inner end side, a film thickness that is reduced toward the inner side. In a semiconductor device manufacturing method for providing such semiconductor device, the high field resistant sealing material is formed in a semiconductor wafer state, then, heat treatment is performed, and after dicing is performed, a chip is mounted.Type: ApplicationFiled: December 26, 2014Publication date: December 7, 2017Inventors: Kan YASUI, Kazuhiro SUZUKI, Takafumi TANIGUCHI
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Publication number: 20170229469Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: ApplicationFiled: April 28, 2017Publication date: August 10, 2017Inventors: Tsutomu OKAZAKI, Daisuke OKADA, Kyoya NITTA, Toshihiro TANAKA, Akira KATO, Toshikazu MATSUI, Yasushi ISHII, Digh HISAMOTO, Kan YASUI
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Patent number: 9640546Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: GrantFiled: January 30, 2015Date of Patent: May 2, 2017Assignee: Renesas Electronics CorporationInventors: Tsutomu Okazaki, Daisuke Okada, Kyoya Nitta, Toshihiro Tanaka, Akira Kato, Toshikazu Matsui, Yasushi Ishii, Digh Hisamoto, Kan Yasui
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Patent number: 9412750Abstract: A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.Type: GrantFiled: March 11, 2016Date of Patent: August 9, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Digh Hisamoto, Shinichiro Kimura, Kan Yasui, Nozomu Matsuzaki
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Publication number: 20160197091Abstract: A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.Type: ApplicationFiled: March 11, 2016Publication date: July 7, 2016Inventors: Digh HISAMOTO, Shinichiro KIMURA, Kan YASUI, Nozomu MATSUZAKI
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Patent number: 9299715Abstract: A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.Type: GrantFiled: April 13, 2015Date of Patent: March 29, 2016Assignee: Renesas Electronics CorporationInventors: Digh Hisamoto, Shinichiro Kimura, Kan Yasui, Nozomu Matsuzaki