Abstract: The disclosure provides a memory device which includes a plurality of word lines grouped into a plurality of WL sets; and a plurality of redundant word lines grouped into M RWL sets; and a memory control circuit connected to the WL sets and the RWL sets and configured to replace a plurality of defective WL sets of the plurality WL sets by selecting from the RWL sets, wherein each of the plurality of defective WL sets comprises at least a defective word line, all of the M RWL sets are available for repairing the WL sets during a wafer stage, where M is an integer greater than 2, and N of M RWL sets is available for repairing the WL sets during the wafer stage, during a package stage and during a post package stage, where N is an integer less than M.

Abstract: The disclosure provides a memory device which includes a plurality of word lines grouped into a plurality of WL sets; and a plurality of redundant word lines grouped into M RWL sets; and a memory control circuit connected to the WL sets and the RWL sets and configured to replace a plurality of defective WL sets of the plurality WL sets by selecting from the RWL sets, wherein each of the plurality of defective WL sets comprises at least a defective word line, all of the M RWL sets are available for repairing the WL sets during a wafer stage, where M is an integer greater than 2, and N of M RWL sets is available for repairing the WL sets during the wafer stage, during a package stage and during a post package stage, where N is an integer less than M.

Abstract: A shift register circuit including a flip-flop chain and a control circuit is provided. The flip-flop chain is configured to receive an input signal and output an output signal. The control circuit is coupled to the flip-flop chain. The control circuit is configured to receive the input signal and the output signal and output a control signal to activate the flip-flop chain according to edge transitions of the input signal and the output signal. In addition, a method for controlling a shift register circuit is also provided.

Abstract: A memory device including a memory unit and a control circuit is provided. The memory unit includes a plurality of memory banks. The memory banks are at least divided into a first group and a second group. The control circuit is coupled to the memory unit. The control circuit is configured to perform a first refresh operation on the first group and the second group. When the control circuit performs the first refresh operation on one of the first group and the second group, the control circuit performs a second refresh operation on a victim row of the other one of the first group and the second group. In addition, a method for refreshing a memory device is also provided.

Abstract: A memory device including a memory unit and a control circuit is provided. The memory unit includes a plurality of memory banks. The memory banks are at least divided into a first group and a second group. The control circuit is coupled to the memory unit. The control circuit is configured to perform a first refresh operation on the first group and the second group. When the control circuit performs the first refresh operation on one of the first group and the second group, the control circuit performs a second refresh operation on a victim row of the other one of the first group and the second group. In addition, a method for refreshing a memory device is also provided.

Abstract: A refresh testing circuit and method are provided. The refresh testing circuit includes an internal clock generator, a counter, and an address detection circuit. The internal clock generator transmits a control clock signal to a refresh controller to generate a bank selection signal and a row address signal for a refresh operation. The counter counts variations of the bank selection signal to generate a count value. The address detection circuit detects whether a value of the row address signal is sequentially increased during the refresh operations to generate a detection signal.