Abstract: According to one embodiment, a memory device includes a plurality of first conductors stacked along a first direction; a second, third, and fourth conductor stacked in a same layer above the first conductors; a plurality of fifth conductors stacked along the first direction; a sixth conductor stacked above the fifth conductors; a first semiconductor extending along the first direction between the second conductor and the sixth conductor; a second semiconductor extending along the first direction between the third conductor and the sixth conductor; and a third semiconductor extending along the first direction between the fourth conductor and the sixth conductor.

Abstract: A storage device includes a first conductor, a resistance variable film, and a second conductor. The resistance variable film includes a first layer and a second layer. The second layer is located on a side opposite to the first conductor with respect to the first layer, contains oxygen, and has conductivity higher than that of the first layer. The second conductor includes a first portion and a second portion. The first portion abuts on the second layer of the resistance variable film. The second portion is separated from the resistance variable film as compared to the first portion. The oxygen content of the first portion is higher than that of the second portion.

Abstract: A storage device includes a first conductor, a resistance variable film, and a second conductor. The resistance variable film includes a first layer and a second layer. The second layer is located on a side opposite to the first conductor with respect to the first layer, contains oxygen, and has conductivity higher than that of the first layer. The second conductor includes a first portion and a second portion. The first portion abuts on the second layer of the resistance variable film. The second portion is separated from the resistance variable film as compared to the first portion. The oxygen content of the first portion is higher than that of the second portion.

Abstract: A nonvolatile semiconductor memory device includes a first wiring layer, multiple second wiring layers provided above the first wiring layer and arrayed along a direction perpendicular to a semiconductor substrate, a semiconductor layer extending along the direct ion and electrically connected to the first wiring layer, a first insulating layer extending along the direction and provided between the semiconductor layer and the multiple second wiring layers, a first oxide layer extending along the direction and provided between the first insulating layer and the multiple second wiring layers, and multiple second oxide layers having first sides being respectively in contact with the multiple second wiring layers and having second sides being in contact with the first oxide layer, a resistance value of a stacked film configured with the first oxide layer and the multiple second oxide layers varying according to a voltage being applied to the multiple second wiring layers.

Abstract: According to one or more embodiments, a memory device includes a first interconnection extending in a first direction, a plurality of second interconnections extending in a second direction intersecting the first direction, and a first resistance change film provided between the first interconnection and the second interconnections. The first resistance change film includes a first conductive layer having a first conductivity, and a second conductive layer provided between the first conductive layer and the plurality of second interconnections and having a second conductivity higher than the first conductivity.

Abstract: According to one or more embodiments, a memory device includes a first interconnection extending in a first direction, a plurality of second interconnections extending in a second direction intersecting the first direction, and a first resistance change film provided between the first interconnection and the second interconnections. The first resistance change film includes a first conductive layer having a first conductivity, and a second conductive layer provided between the first conductive layer and the plurality of second interconnections and having a second conductivity higher than the first conductivity.

Abstract: A non-volatile memory device includes a first semiconductor body extending in a first direction, an electrode extending in a second direction intersecting the first direction, a charge storage layer provided between the first semiconductor body and the electrode, and a first insulating layer provided between the electrode and the charge storage layer. The electrode includes a first layer, a second layer and a third layer. The first layer is provided on the first insulating layer and includes tungsten. The second layer is provided on the first layer and includes tungsten nitride. The third layer is provided on the second layer and includes tungsten.

Abstract: A method for manufacturing a semiconductor device includes forming a metal-containing layer over a semiconductor substrate, forming an insulating film to cover the semiconductor substrate and the metal-containing layer, forming a first contact hole that penetrates through the insulating film to reach the semiconductor substrate, forming a second contact hole that penetrates through the insulating film to reach the metal-containing layer, forming a first conductive plug on a portion, exposed through the first contact hole, of the semiconductor substrate and including a first material, forming a second conductive plug on the first conductive plug and including a second material, the semiconductor substrate being closer to a lower surface of the second conductive plug than to an upper surface of the metal-containing layer, and forming a third conductive plug on a portion, exposed through the second contact hole, of the metal-containing layer, the third conductive plug including a third material.

Abstract: A semiconductor device including semiconductor substrate having an active region and an element isolation region, the active region isolated by the element isolation region, the element isolation region provided with an element isolation trench; a memory-cell transistor formed above the semiconductor substrate and having a gate electrode formed above the active region via a first insulating film, the gate electrode formed of a stack including a floating gate electrode, a first interelectrode insulating film, and a control gate electrode; an element isolation insulating film filled in the element isolation trench; and a second interelectrode insulating film disposed above the element isolation insulating film so as to form a stack of the second interelectrode insulating film and the control electrode above the element isolation insulating and a dielectric constant of the second interelectrode insulating film being higher than a dielectric constant of the first interelectrode insulating film.