Patents by Inventor Kanad Chakraborty
Kanad Chakraborty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9728273Abstract: In one embodiment, a BIST (built-in self-test) engine performs BIST testing of embedded memory in an integrated circuit device (e.g., an FPGA) via an (e.g., hard-wired, dedicated, low-latency) bus from the configuration bitstream engine. During BIST testing, data is written into the embedded memory at-speed, which may require the bitstream engine to produce a higher frequency than originally used for configuration. Between consecutive write operations, the BIST engine is capable of reading the previously written set of data from the embedded memory and comparing that read-back data with the corresponding original set of data to determine whether a BIST error has occurred. By performing back-to-back write/read-back operations faster than the configuration speed and using a dedicated W/RB bus, BIST testing can be optimally performed without false-positive-invoking delays and undesirable resource utilization.Type: GrantFiled: May 21, 2014Date of Patent: August 8, 2017Assignee: Lattice Semiconductor CorporationInventors: Kanad Chakraborty, Naveen Purushotham
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Patent number: 9618579Abstract: In certain embodiments, an integrated circuit has scan-test circuitry that performs scan testing on circuitry under scan test (CUST) within the IC, where the scan-test circuitry is susceptible to a defect. In order to enable the defect to be corrected after it occurs, the scan-test circuitry includes a set of programmable circuitry connected to provide a signal to other circuitry (e.g., a scan chain) within the scan-test circuitry, where the set of programmable circuitry includes one or more configurable memory cells connected to control the programming of the set of programmable circuitry. The memory cell(s) can be configured to program the set of programmable circuitry to enable the scan testing to be performed without modification. The memory cell(s) can also be configured to program the set of programmable circuitry to modify the scan testing to correct the defect in the scan-test circuitry.Type: GrantFiled: April 28, 2015Date of Patent: April 11, 2017Assignee: Lattice Semiconductor CorporationInventor: Kanad Chakraborty
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Patent number: 9530486Abstract: In one embodiment, a memory array has a pair of bit lines for each column of 1-bit SRAM cells and a word line for each row of cells, where, during a memory read operation, the bit value stored in each cell is detectable by sensing a voltage difference developed between the corresponding bit line pair. A first signal-development circuit is coupled to one bit line to accelerate draining that bit line of charge if a first bit value is stored in the cell, and a second signal-development circuit is coupled to the other bit line to accelerate draining that other bit line of charge if a second, different bit value is stored in the cell. Pulldown devices are provided to ensure that the signal-development circuit operate properly during the pre-charge and voltage difference development phases of the memory read operation, which is now faster due to the signal-development circuits.Type: GrantFiled: October 7, 2015Date of Patent: December 27, 2016Assignee: LATTICE SEMICONDUCTOR CORPORATIONInventor: Kanad Chakraborty
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Publication number: 20160320448Abstract: In certain embodiments, an integrated circuit has scan-test circuitry that performs scan testing on circuitry under scan test (OUST) within the IC, where the scan-test circuitry is susceptible to a defect. In order to enable the defect to be corrected after it occurs, the scan-test circuitry includes a set of programmable circuitry connected to provide a signal to other circuitry (e.g., a scan chain) within the scan-test circuitry, where the set of programmable circuitry includes one or more configurable memory cells connected to control the programming of the set of programmable circuitry. The memory cell(s) can be configured to program the set of programmable circuitry to enable the scan testing to be performed without modification. The memory cell(s) can also be configured to program the set of programmable circuitry to modify the scan testing to correct the defect in the scan-test circuitry.Type: ApplicationFiled: April 28, 2015Publication date: November 3, 2016Inventor: Kanad Chakraborty
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Publication number: 20150340103Abstract: In one embodiment, a BIST (built-in self-test) engine performs BIST testing of embedded memory in an integrated circuit device (e.g., an FPGA) via an (e.g., hard-wired, dedicated, low-latency) bus from the configuration bitstream engine. During BIST testing, data is written into the embedded memory at-speed, which may require the bitstream engine to produce a higher frequency than originally used for configuration. Between consecutive write operations, the BIST engine is capable of reading the previously written set of data from the embedded memory and comparing that read-back data with the corresponding original set of data to determine whether a BIST error has occurred. By performing back-to-back write/read-back operations faster than the configuration speed and using a dedicated W/RB bus, BIST testing can be optimally performed without false-positive-invoking delays and undesirable resource utilization.Type: ApplicationFiled: May 21, 2014Publication date: November 26, 2015Applicant: Lattice Semiconductor CorporationInventors: Kanad Chakraborty, Naveen Purushotham
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Publication number: 20150310933Abstract: In certain embodiment, built-in self-test (BIST) circuitry for multiport memory comprises a configurable address generator and a configurable data generator. The configurable address generator can be configured to concurrently generate first and second logical memory addresses corresponding to physically neighboring first and second memory cells of the multiport memory for any selected memory mode of a plurality of available memory modes having different column-multiplexing schemes. The configurable data generator can be configured to concurrently generate two sets of data for the selected memory mode, such that (i) the first set of data is written into and read from the multiport memory via a first memory port using the first logical memory address and (ii) the second set of data is written into and read from the multiport memory via a second memory port using the second logical memory address. The BIST circuitry enables efficient, physically aware built-in self-testing.Type: ApplicationFiled: September 10, 2014Publication date: October 29, 2015Inventors: Naveen Purushotham, Kanad Chakraborty, Daniel Ratchen
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Patent number: 8977917Abstract: In one embodiment, an integrated circuit chip has an input/output (I/O) interface and programmable fabric. The I/O interface restricts access to scan testing of the chip by requiring (1) a specific scan-testing instruction, (2) a specific manufacturing key, and (3) a specific fabric pattern value from a specific set of registers in the programmed fabric. In addition or alternatively, the I/O interface has circuitry that enables scan testing of most of the logic of the I/O interface itself, including the logic being driven by the JTAG TAP state register.Type: GrantFiled: April 8, 2013Date of Patent: March 10, 2015Assignee: Lattice Semiconductor CorporationInventors: Wei Han, Zheng Chen, Eric Lee, Jie Qin, Shankar Durgamahanthi, Kanad Chakraborty, Dan Ratchen
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Publication number: 20140136914Abstract: In one embodiment, an integrated circuit chip has an input/output (I/O) interface and programmable fabric. The I/O interface restricts access to scan testing of the chip by requiring (1) a specific scan-testing instruction, (2) a specific manufacturing key, and (3) a specific fabric pattern value from a specific set of registers in the programmed fabric. In addition or alternatively, the I/O interface has circuitry that enables scan testing of most of the logic of the I/O interface itself, including the logic being driven by the JTAG TAP state register.Type: ApplicationFiled: April 8, 2013Publication date: May 15, 2014Applicant: Lattice Semiconductor CorporationInventors: Wei Han, Zheng Chen, Eric Lee, Jie Qin, Shankar Durgamahanthi, Kanad Chakraborty, Dan Ratchen
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Patent number: 7511535Abstract: A power management circuit is provided for controlling power dissipation in at least one combinational logic circuit. The power management circuit includes a detector operative to receive at least a first input signal to the combinational logic circuit and to detect a transition of the first input signal between a first logic state and a second logic state. The detector generates a control signal indicative of whether or not a transition of the first input signal has occurred.Type: GrantFiled: February 28, 2007Date of Patent: March 31, 2009Assignee: Agere Systems Inc.Inventors: Kanad Chakraborty, Steven E. Strauss, Bingxiong Xu
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Publication number: 20080204124Abstract: A power management circuit is provided for controlling power dissipation in at least one combinational logic circuit. The power management circuit includes a detector operative to receive at least a first input signal to the combinational logic circuit and to detect a transition of the first input signal between a first logic state and a second logic state. The detector generates a control signal indicative of whether or not a transition of the first input signal has occurred.Type: ApplicationFiled: February 28, 2007Publication date: August 28, 2008Inventors: Kanad Chakraborty, Steven E. Strauss, Bingxiong Xu
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Patent number: 7409659Abstract: A static latch circuit is used to suppress crosstalk glitch in a synchronous digital integrated circuit. A static latch is inserted into a selected victim net, and the net is examined if crosstalk glitch induced in the selected victim net is sufficiently suppressed. If not, then the selected victim net is examined to check whether the crosstalk glitch is primarily due to propagated noise from an earlier stage or due to noise injected in the selected victim net. If the crosstalk glitch is propagated from an earlier stage, then a second static latch is inserted before the state in which the first static latch is inserted. Alternatively, another static latch may be inserted in the selected victim net. Cell libraries including a variety of static latch circuit architectures can be designed.Type: GrantFiled: November 12, 2004Date of Patent: August 5, 2008Assignee: Agere Systems Inc.Inventors: Kanad Chakraborty, Thaddeus J. Gabara, Kevin R. Stiles, Bingxiong Xu
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Publication number: 20070194453Abstract: An integrated circuit includes a first semiconductor chip including one or more circuits thereon performing substantially core logic functions, the first semiconductor chip including multiple signal pads for providing electrical connection to the one or more circuits. The integrated circuit further includes at least a second semiconductor chip including one or more circuits thereon performing substantially input/output interface functions, the second semiconductor chip including multiple signal pads for providing electrical connection to the one or more circuits on the first semiconductor chip. The signal pads on the second semiconductor chip are substantially aligned with and electrically connected to corresponding signal pads on the first semiconductor chip.Type: ApplicationFiled: January 27, 2006Publication date: August 23, 2007Inventors: Kanad Chakraborty, Bingxiong Xu, Xingling Zhou
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Publication number: 20060107245Abstract: A static latch circuit is used to suppress crosstalk glitch in a synchronous digital integrated circuit. A static latch is inserted into a selected victim net, and the net is examined if crosstalk glitch induced in the selected victim net is sufficiently suppressed. If not, then the selected victim net is examined to check whether the crosstalk glitch is primarily due to propagated noise from an earlier stage or due to noise injected in the selected victim net. If the crosstalk glitch is propagated from an earlier stage, then a second static latch is inserted before the state in which the first static latch is inserted. Alternatively, another static latch may be inserted in the selected victim net. Cell libraries including a variety of static latch circuit architectures can be designed.Type: ApplicationFiled: November 12, 2004Publication date: May 18, 2006Inventors: Kanad Chakraborty, Thaddeus Gabara, Kevin Stiles, Bingxiong Xu
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Patent number: 7047163Abstract: A method (and system) of applying transforms for modifying a plurality of domains concurrently in a design space, includes creating a sequence of more and less granular placement and netlist modification transforms. A converging design process flow is created by a flexible mechanism in which a select combination of fine-grained transforms are applied to optimize the netlist and placement of a design.Type: GrantFiled: March 13, 2000Date of Patent: May 16, 2006Assignee: International Business Machines CorporationInventors: Kanad Chakraborty, Wilm Ernst Donath, Prabhakar Nandavar Kudva, Lakshmi Narasimha Reddy, Leon Stok, Andrew James Sullivan, Paul Gerard Villarrubia
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Patent number: 6532578Abstract: A method of configuring partitions for different circuit or other operational areas on an integrated circuit initially identifies points representing components of an integrated circuit with respect to a coordinate system having a horizontal axis and a vertical axis, and subsequently creates a first isothetic rectangular partition containing all of the identified points of the integrated circuit. The method then continues by subdividing the first isothetic rectangular partition with respect to the horizontal axis by creating a plurality of isothetic rectangular sub-partitions collectively containing all of the identified points of the integrated circuit. Each of the isothetic rectangular sub-partitions is separated by a line parallel to the horizontal axis. These isothetic rectangular sub-partitions collectively encompass a minimum area containing all of the identified points.Type: GrantFiled: May 16, 2001Date of Patent: March 11, 2003Assignee: International Business Machines CorporationInventors: Kanad Chakraborty, Maharaj Mukherjee
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Publication number: 20020174410Abstract: A method of configuring partitions for different circuit or other operational areas on an integrated circuit initially identifies points representing components of an integrated circuit with respect to a coordinate system having a horizontal axis and a vertical axis, and subsequently creates a first isothetic rectangular partition containing all of the identified points of the integrated circuit. The method then continues by subdividing the first isothetic rectangular partition with respect to the horizontal axis by creating a plurality of isothetic rectangular sub-partitions collectively containing all of the identified points of the integrated circuit. Each of the isothetic rectangular sub-partitions is separated by a line parallel to the horizontal axis. These isothetic rectangular sub-partitions collectively encompass a minimum area containing all of the identified points.Type: ApplicationFiled: May 16, 2001Publication date: November 21, 2002Applicant: International Business Machines CorporationInventors: Kanad Chakraborty, Maharaj Mukherjee