Patents by Inventor Kanad D. Kanhere

Kanad D. Kanhere has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9047188
    Abstract: In the L2 FIFO architecture incoming frames are stored in a multi bank FIFO to enable offloading the programmable real-time unit to do other tasks. The L2 FIFO buffers data coming from the L1 FIFO, reducing the polling time for received data. Status is always checked for errors before processing the data and updating the state variables. Implementing a state machine to perform some of the checks results in a PRU utilization that is not a function of the bytes that need to be processed.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: June 2, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pratheesh Gangadhar Thalakkal Kottilaveedu, Kanad D. Kanhere
  • Publication number: 20140101496
    Abstract: In the L2 FIFO architecture incoming frames are stored in a multi bank FIFO to enable offloading the programmable real-time unit to do other tasks. The L2 FIFO buffers data coming from the L1 FIFO, reducing the polling time for received data. Status is always checked for errors before processing the data and updating the state variables. Implementing a state machine to perform some of the checks results in a PRU utilization that is not a function of the bytes that need to be processed.
    Type: Application
    Filed: October 4, 2013
    Publication date: April 10, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Pratheesh Gangadhar Thalakkal Kottilaveedu, Kanad D. Kanhere