Patents by Inventor Kanae Fujii

Kanae Fujii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5679973
    Abstract: A lateral Hall element includes a substrate, a first-conductivity type active layer formed on the substrate, a first second-conductivity type semiconductor layer formed to surround the first-conductivity type active layer and formed to a depth to reach the substrate, a pair of first first-conductivity type semiconductor layers of high impurity concentration selectively formed with a preset distance apart from each other on the surface of the first-conductivity type active layer, current supply electrodes respectively formed on the pair of first first-conductivity type semiconductor layers, a pair of second first-conductivity type semiconductor layers of high impurity concentration formed with a preset distance apart from each other on the surface of the first-conductivity type active layer in position different from the first first-conductivity type semiconductor layers, sensor electrodes respectively formed on the pair of second first-conductivity type semiconductor layers, and a plurality of second second-c
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: October 21, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Mochizuki, Kanae Fujii, Hideyuki Funaki
  • Patent number: 5548151
    Abstract: In a Hall element, a semiconductor layer is surrounded by a first trench filled with an insulator. A first current supply portion of an n+-type semiconductor is disposed adjacent the semiconductor layer and the first trench. Second current supply portions are also disposed adjacent the semiconductor layer and the first trench and symmetrical with respect to the first current supply portion. Sensor portions of an n+-type semiconductor are disposed adjacent the semiconductor layer and the first trench at about the center between the first and second current supply portions, respectively. A magnetic flux perpendicular to the upper surface of the semiconductor layer can be detected by the foregoing arrangement.
    Type: Grant
    Filed: February 7, 1995
    Date of Patent: August 20, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki Funaki, Hiroshi Mochizuki, Ryoji Maruyama, Kanae Fujii