Abstract: A method of measuring threshold voltage variation using a device array provides accurate threshold voltage distribution values for process verification and improvement. The characterization array imposes a fixed drain-source voltage and a constant channel current at individual devices within the array. Another circuit senses the source voltage of the individual device within the array. The statistical distribution of the threshold voltage is determined directly from the source voltage distribution by offsetting each source voltage by a value determined by completely characterizing one or more devices within the array. The resulting methodology avoids the necessity of otherwise characterizing each device within the array, thus reducing measurement time dramatically.

Abstract: A scannable virtual rail ring oscillator circuit and system for measuring variations in device characteristics provides the ability to study random device characteristic variation as well as systematic differences between N-channel and P-channel devices using a ring oscillator frequency measurement. The ring oscillator is operated from at least one virtual power supply rail that is connected to the actual power supply rail by a plurality of transistors controlled by a programmable source. The transistors are physically distributed along the physical distribution of the ring oscillator elements and each can be enabled in turn and the variation in ring oscillator frequency measured. The ring oscillator frequency measurements yield information about the variation between the transistors and N-channel vs. P-channel variation can be studied by employing positive and negative virtual power supply rails with corresponding P-channel and N-channel control transistors.

Abstract: A contour of a mask design for an integrated circuit is modified to compensate for systematic variations arising from non-optical effects such as stress, well proximity, rapid thermal anneal, or spacer thickness. Electrical characteristics of a simulated integrated circuit chip fabricated using the mask design are extracted and compared to design specifications, and one or more edges of the contour are adjusted to reduce the systematic variation until the electrical characteristic is within specification. The particular electrical characteristic preferably depends on which layer is to be fabricated from the mask: on-current for a polysilicon; resistance for contact; resistance and capacitance for metal; current for active; and resistance for vias. For systematic threshold voltage variation, the contour is adjusted to match a gate length which corresponds to an on-current value according to pre-calculated curves for contour current and gate length at a nominal threshold voltage of the chip.

Abstract: A moment-based method and system for evaluation of metal layer transient currents in an integrated circuit provides a computationally efficient evaluation of transient current magnitudes through each interconnect in the metal layer. The determinable magnitudes include peak, rms and average current, which can be used in subsequent reliability analyses. Interconnect path nodes are traversed and circuit moments are either retrieved from a previous interconnect delay analysis or are computed. For each pair of nodes, current moments are computed from the circuit moments. The average current is computed from the zero-order circuit moment and the peak and rms currents are obtained from expressions according to a lognormal or other distribution shape assumption for the current waveform at each node.

Abstract: Measurement of individual quiescent supply currents from multiple power supply pads located across a semiconductor die provides a means of characterizing across-die variation. A ratio is created by combining the individual pad supply current with the sum of all pad supply currents for a given die. An n-tuple is formed from the set of ratios for all pad supply currents to provide a unique signature for different across-die variation profiles.

Abstract: The present invention provides a method for measuring statistics of dynamic random access memory (DRAM) process parameters for improving yield and performance of a DRAM. The basic principles for measuring capacitance are similar to charge based capacitance (CBCM), however the present invention differs in several fundamental aspects. In one embodiment, the method includes receiving a selection of a storage cell of the DRAM; measuring a storage cell capacitance (Ccell) of the storage cell; measuring a local bitline capacitance (Cbl) of the storage cell; measuring a transfer device voltage (VT) of the storage cell; computing a transfer ratio (TR) for the storage cell; and measuring a data retention time for the storage cell.

Abstract: A pulsed dynamic logic environment metric measurement circuit provides self-referenced, low area/cost and low power measurement of circuit environment metrics, such as supply voltage. A cascade of dynamic logic stages is clocked with a pulse having a width substantially independent of an environment metric to which the delay of the dynamic logic stages is sensitive. The number of dynamic logic stages that evaluate within a given pulse provides a direct measure of the pulse width, and thus the value of the circuit metric. The pulse may be generated from a logical exclusive-OR combination of a clock signal provided from two circuit paths that differ in sensitivity to the environment metric to be measured. One circuit path may have a delay substantially determined only by wire delay, which is not substantially sensitive to circuit environment metrics such as power supply voltage.

Abstract: A test structure for statistical characterization of local device mismatches contains densely populated SRAM devices arranged in a row/column addressable array that enables resource sharing of many devices. The test structure includes a built-in sensing mechanism to calibrate or null out sources of error, and current steering to avoid negative effects of current leakage along spurious paths. The gate and drain lines of each column are driven from both the top and bottom to minimizes parasitic effects. The system can handle a large number of devices while still providing high spatial resolution of current measurements.

Abstract: A method and test circuit provide measurements to aid in the understanding of time-varying threshold voltage changes such as negative bias temperature instability and positive bias temperature instability. In order to provide accurate measurements during an early stage in the threshold variation, a current generating circuit is integrated on a substrate with the device under test, which may be a device selected from among an array of devices. The current generating circuit may be a current mirror that responds to an externally-supplied current provided by a test system. A voltage source circuit may be included to hold the drain-source voltage of the transistor constant, although not required. A stress is applied prior to the measurement phase, which may include a controllable relaxation period after the stress is removed.

Abstract: A digital circuit with dynamic power and performance control via per-block selectable operating voltage level permits dynamic tailoring of operating power to processing demand and/or compensation for process variation. A set of processing blocks having a power supply selectable from two different power supply voltage levels is provided. The power level of the overall circuit is set by selecting the power supply voltage for each block to yield a combination of blocks that meets operating requirements. Alternatively, one circuit per pair from a set of pairs of redundant logic blocks supplied by the different power supply voltage levels can be selected to meet the operating requirements. The unselected blocks can be disabled by disabling foot devices or disabling transitions at the inputs to the unselected blocks. Performance measurement and feedback circuits can be included to tune the power consumption and performance level of the circuit to meet an expected level.

Abstract: A characterization array circuit provides accurate threshold voltage distribution values for process verification and improvement. The characterization array includes a circuit for imposing a fixed drain-source voltage and a constant channel current at individual devices within the array. A circuit for sensing the source voltage of the individual device is also included within the array. The statistical distribution of the threshold voltage is determined directly from the source voltage distribution by offsetting each source voltage by a value determined by completely characterizing one or more devices within the array. The resulting methodology avoids the necessity of otherwise characterizing each device within the array, thus reducing measurement time dramatically.

Abstract: A method and system for isolating dopant fluctuation and device length variation from statistical measurements of threshold voltage provides fast determination of process variation for devices in a characterization array. Statistics of threshold voltage are measured at two different values of drain-source voltage imposed on the devices in the characterization array. At least one moment of the a drain-induced barrier lowering (DIBL) coefficient ?, which is a measure of device length and zero-bias threshold voltage VTH0 are computed directly from the statistical moment values of the threshold variation. The standard deviation and mean of ? and VTH0 can thereby be obtained having only a statistical description of the threshold voltage for the devices in the array at multiple drain-source voltages. The threshold voltage statistics can be obtained from a digital meter measurement (rms and DC average) of a waveform indicative of threshold voltage produced by sequentially selecting the array devices.

Abstract: A method and test system for fast determination of parameter variation statistics provides a mechanism for determining process variation and parameter statistics using low computing power and readily available test equipment. A test array having individually selectable devices is stimulated under computer control to select each of the devices sequentially. A test output from the array provides a current or voltage that dependent on a particular device parameter. The sequential selection of the devices produces a voltage or current waveform, characteristics of which are measured using a digital multi-meter that is interfaced to the computer. The rms value of the current or voltage at the test output is an indication of the standard deviation of the parameter variation and the DC value of the current or voltage is an indication of the mean value of the parameter.

Abstract: A test circuit for fast determination of device capacitance variation statistics provides a mechanism for determining process variation and parameter statistics using low computing power and readily available test equipment. A test array having individually selectable devices is stimulated under computer control to select each of the devices sequentially. A test output from the array provides a current or voltage that dependent on a particular device parameter. The sequential selection of the devices produces a voltage or current waveform, characteristics of which are measured using a digital multi-meter that is interfaced to the computer. The rms value of the current or voltage at the test output is an indication of the standard deviation of the parameter variation and the DC value of the current or voltage is an indication of the mean value of the parameter.

Abstract: An error detection circuit for a latch precharges two dynamic nodes whose discharge paths are gated by true and complement storage nodes of the latch, such that one and only one of the dynamic nodes always discharges when the clock signal transitions from an active state to an inactive state. If a soft error flips the contents of the latch during storage mode the other dynamic node will discharge. A gate having inputs coupled to the dynamic nodes produces an error signal when both nodes have discharged. The error signal can then be used to select between true and complement outputs of the latch. The invention can be implemented in a more robust embodiment which examines the outputs of two error detection circuits to generate a combined error signal that ensures against false error detection when an upset occurs within one of the detection circuits.

Abstract: Measurement of individual quiescent supply currents from multiple power supply pads located across a semiconductor die provides a means of characterizing across-die variation. A ratio is created by combining the individual pad supply current with the sum of all pad supply currents for a given die. An n-tuple is formed from the set of ratios for all pad supply currents to provide a unique signature for different across-die variation profiles.

Abstract: A scannable virtual rail ring oscillator circuit and system for measuring variations in device characteristics provides the ability to study random device characteristic variation as well as systematic differences between N-channel and P-channel devices using a ring oscillator frequency measurement. The ring oscillator is operated from at least one virtual power supply rail that is connected to the actual power supply rail by a plurality of transistors controlled by a programmable source. The transistors are physically distributed along the physical distribution of the ring oscillator elements and each can be enabled in turn and the variation in ring oscillator frequency measured. The ring oscillator frequency measurements yield information about the variation between the transistors and N-channel vs. P-channel variation can be studied by employing positive and negative virtual power supply rails with corresponding P-channel and N-channel control transistors.

Abstract: A scannable virtual rail method and ring oscillator circuit for measuring variations in device characteristics provides the ability to study random device characteristic variation as well as systematic differences between N-channel and P-channel devices using a ring oscillator frequency measurement. The ring oscillator is operated from at least one virtual power supply rail that is connected to the actual power supply rail by a plurality of transistors controlled by a programmable source. The transistors are physically distributed along the physical distribution of the ring oscillator elements and each can be enabled in turn and the variation in ring oscillator frequency measured. The ring oscillator frequency measurements yield information about the variation between the transistors and N-channel vs. P-channel variation can be studied by employing positive and negative virtual power supply rails with corresponding P-channel and N-channel control transistors.

Abstract: A pulsed dynamic logic environment metric measurement circuit provides self-referenced, low area/cost and low power measurement of circuit environment metrics, such as supply voltage. A cascade of dynamic logic stages is clocked with a pulse having a width substantially independent of an environment metric to which the delay of the dynamic logic stages is sensitive. The number of dynamic logic stages that evaluate within a given pulse provides a direct measure of the pulse width, and thus the value of the circuit metric. The pulse may be generated from a logical exclusive-OR combination of a clock signal provided from two circuit paths that differ in sensitivity to the environment metric to be measured. One circuit path may have a delay substantially determined only by wire delay, which is not substantially sensitive to circuit environment metrics such as power supply voltage.

Abstract: A IC wafer is fabricated using a process of interest to have a plurality of FET devices with different channel lengths (Leff) form a plurality of channel length groups. The threshold voltage (VT) is measured of a statistical sample of the FET devices in each channel length group at two different drain-to-source voltage (VDS). The mean of VT is calculated for each channel length and each VDS. A slope coefficient ? relating VT to Leff is calculated at each VDS. The total variance of VT is calculated at each VDS. Two equations at each VDS, each relating the total variance of VT to the variance of VT with respect to dopant levels and the square of the slope coefficient ? times the variance of Leff, are solved simultaneously to obtain the variance of VT with respect to dopant levels and the variance of Leff.