Abstract: A process cycles between etching and passivating chemistries to create rough sidewalls that are converted into small structures. In one embodiment, a mask is used to define lines in a single crystal silicon wafer. The process creates ripples on sidewalls of the lines corresponding to the cycles. The lines are oxidized in one embodiment to form a silicon wire corresponding to each ripple. The oxide is removed in a further embodiment to form structures ranging from micro sharp tips to photonic arrays of wires. Fluidic channels are formed by oxidizing adjacent rippled sidewalls. The same mask is also used to form other structures for MEMS devices.

Abstract: According to some embodiments, an apparatus includes a substrate that defines a plane. The apparatus also includes a first conducting plate that is substantially normal to the substrate and a second conducting plate that is (i) substantially normal to the substrate and (ii) deformable in response to a pressure.

Abstract: A method for forming smooth walled, prismatically-profiled through-wafer vias and articles formed through the method. An etch stop material is provided on a wafer, which may be a <110> silicon wafer. A mask material is provided on the etch stop material and patterned in such a way as to lead to the formation of vias that have at least one pair of opposing side walls that run parallel to a <111> plane in the wafer. A wet etchant, such as potassium hydroxide, is used to etch vias in the wafer. The use of a wet etchant leads to the formation of smooth side walls. This method allows an aspect ratio of height versus width of the vias of greater than 75 to 1.

Abstract: Multi-level structures are formed in a semiconductor substrate by first forming a pattern of lines or structures of different widths. Width information on the pattern is decoded by processing steps into level information to form a MEMS structure. The pattern is etched to form structures having a first floor. The structures are oxidized until structures of thinner width are substantially fully oxidized. A portion of the oxide is then etched to expose the first floor. The first floor is then etched to form a second floor. The oxide is then optionally removed, leaving a multi-level structure. In one embodiment, high aspect ratio comb actuators are formed using the multi-level structure process.

Abstract: A sensor, in accordance with aspects of the present technique, is provided. The sensor comprises a membrane formed of gallium nitride. The membrane is disposed on a substrate, which is wet-etched to form a closed cavity. The membrane exhibits both a capacitive response and a piezo-response to an external stimulus. The sensor further includes a circuit for measuring at least one of the capacitive response or the piezo-response. In certain aspects, the sensor may be operable to measure external stimuli, such as, pressure, force and mechanical vibration.

Abstract: A method for forming smooth walled, prismatically-profiled through-wafer vias and articles formed through the method. An etch stop material is provided on a wafer, which may be a <110> silicon wafer. A mask material is provided on the etch stop material and patterned in such a way as to lead to the formation of vias that have at least one pair of opposing side walls that run parallel to a <111> plane in the wafer. A wet etchant, such as potassium hydroxide, is used to etch vias in the wafer. The use of a wet etchant leads to the formation of smooth side walls. This method allows an aspect ratio of height versus width of the vias of greater than 75 to 1.

Abstract: Multi-level structures are formed in a semiconductor substrate by first forming a pattern of lines or structures of different widths. Width information on the pattern is decoded by processing steps into level information to form a MEMS structure. The pattern is etched to form structures having a first floor. The structures are oxidized until structures of thinner width are substantially fully oxidized. A portion of the oxide is then etched to expose the first floor. The first floor is then etched to form a second floor. The oxide is then optionally removed, leaving a multi-level structure. In one embodiment, high aspect ratio comb actuators are formed using the multi-level structure process.

Abstract: A process cycles between etching and passivating chemistries to create rough sidewalls that are converted into small structures. In one embodiment, a mask is used to define lines in a single crystal silicon wafer. The process creates ripples on sidewalls of the lines corresponding to the cycles. The lines are oxidized in one embodiment to form a silicon wire corresponding to each ripple. The oxide is removed in a further embodiment to form structures ranging from micro sharp tips to photonic arrays of wires. Fluidic channels are formed by oxidizing adjacent rippled sidewalls. The same mask is also used to form other structures for MEMS devices.

Abstract: A sensor package and method are described. The sensor package includes an enclosure, a diaphragm coupled to the enclosure. The diaphragm is configured to receive vibrations from an ambient environment. Further, the sensor package includes a pressure sensing element disposed inside the enclosure, and a pressure transfer medium disposed inside the enclosure and proximate the pressure sensing element, where the pressure transfer medium includes a fluid, and a plurality of filler particles suspended in the fluid. The filler particles serve to reduce a coefficient of thermal expansion of the pressure transfer medium.

Abstract: According to some embodiments, a conducting layer is formed on a first wafer. An insulating layer is formed on a second wafer. The insulating layer includes a cavity and a conducting area may be formed in the second wafer proximate to the cavity. The side of the conducting layer opposite the first wafer is bonded to the side of the insulating layer opposite the second wafer. At least some of the first wafer is then removed, without removing at least some of the conducting layer, to form a conducting diaphragm that is substantially parallel to the second wafer. In this way, an amount of capacitance between the diaphragm and the conducting area may be measured to determine an amount of pressure being applied to the diaphragm.

Abstract: A method for forming smooth walled, prismatically-profiled through-wafer vias and articles formed through the method. An etch stop material is provided on a wafer, which may be a <110> silicon wafer. A mask material is provided on the etch stop material and patterned in such a way as to lead to the formation of vias that have at least one pair of opposing side walls that run parallel to a <111> plane in the wafer. A wet etchant, such as potassium hydroxide, is used to etch vias in the wafer. The use of a wet etchant leads to the formation of smooth side walls. This method allows an aspect ratio of height versus width of the vias of greater than 75 to 1.

Abstract: According to some embodiments, an apparatus includes a substrate that defines a plane. The apparatus also includes a first conducting plate that is substantially normal to the substrate and a second conducting plate that is (i) substantially normal to the substrate and (ii) deformable in response to a pressure.

Abstract: A process cycles between etching and passivating chemistries to create rough sidewalls that are converted into small structures. In one embodiment, a mask is used to define lines in a single crystal silicon wafer. The process creates ripples on sidewalls of the lines corresponding to the cycles. The lines are oxidized in one embodiment to form a silicon wire corresponding to each ripple. The oxide is removed in a further embodiment to form structures ranging from micro sharp tips to photonic arrays of wires. Fluidic channels are formed by oxidizing adjacent rippled sidewalls. The same mask is also used to form other structures for MEMS devices.

Abstract: Multi-level structures are formed in a semiconductor substrate by first forming a pattern of lines or structures of different widths. Width information on the pattern is decoded by processing steps into level information to form a MEMS structure. The pattern is etched to form structures having a first floor. The structures are oxidized until structures of thinner width are substantially fully oxidized. A portion of the oxide is then etched to expose the first floor. The first floor is then etched to form a second floor. The oxide is then optionally removed, leaving a multi-level structure. In one embodiment, high aspect ratio comb actuators are formed using the multi-level structure process.