Patents by Inventor Kanako Sawada
Kanako Sawada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160079500Abstract: A light emitting device includes a first lead frame having a top surface including a first region and a second region, a first metal layer disposed on the first region of the top surface, a reflector layer in contact with the second region of the top surface, a light emitting element mounted on the first metal layer and electrically connected to the first lead frame, and a transparent resin layer covering the light emitting element and in contact with the first metal layer.Type: ApplicationFiled: March 1, 2015Publication date: March 17, 2016Inventors: Hideo AOKI, Kanako SAWADA, Chiaki TAKUBO
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Patent number: 8409919Abstract: According to a manufacturing method of one embodiment, a first solder bump and a second solder bump are aligned and placed in contact with each other, and thereafter, the first and second solder bumps are heated to a temperature equal or higher than a melting point of the solder bumps and melted, whereby a partially connection body of the first solder bump and the second solder bump is formed. The partially connection body is cooled. The cooled partially connection body is heated to a temperature equal to or higher than the melting point of the solder bump in a reducing atmosphere, thereby to form a permanent connection body by melting the partially connection body while removing an oxide film existing on a surface of the partially connection body.Type: GrantFiled: September 15, 2010Date of Patent: April 2, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Hideo Aoki, Masatoshi Fukuda, Kanako Sawada, Yasuhiro Koshio
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Patent number: 8191758Abstract: In one embodiment, a first substrate having first solder bumps and a second substrate having second solder bumps are stacked while temporarily tacking the solder bumps to each other, and then a stack is disposed inside a furnace. The gas in the furnace is exhausted to be in a reduced pressure atmosphere, and then a carboxylic acid gas is introduced into the furnace. While increasing a temperature inside the furnace where the carboxylic acid gas is introduced, the gas in the furnace is exhausted to be in a reduced pressure atmosphere at a temperature in a range from a reduction temperature of oxide films by the carboxylic acid gas to lower than a melting temperature of the solder bumps. By increasing the temperature inside the furnace up to a temperature in a range of the melting temperature of the solder bumps and higher, the first solder bumps and the second solder bumps are melted and joined.Type: GrantFiled: June 15, 2010Date of Patent: June 5, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Kanako Sawada, Hideo Aoki, Naoyuki Komuta, Koji Ogiso
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Publication number: 20110175204Abstract: According to one embodiment, a manufacturing method of a semiconductor device is disclosed. This method can include dicing along a predetermined line a laminated substrate which has a first substrate and a second substrate, one of which is made of a semiconductor substrate, mutually adhered with an adhesive layer interposed between them. The dicing process includes irradiating a laser beam to the adhesive layer along the dicing line to form scribe lines corresponding to the dicing line on the first and second substrates. And, the dicing process includes applying an impact to the laminated substrate to divide along the scribe lines.Type: ApplicationFiled: January 13, 2011Publication date: July 21, 2011Inventor: Kanako SAWADA
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Publication number: 20110076801Abstract: According to a manufacturing method of one embodiment, a first solder bump and a second solder bump are aligned and placed in contact with each other, and thereafter, the first and second solder bumps are heated to a temperature equal or higher than a melting point of the solder bumps and melted, whereby a partially connection body of the first solder bump and the second solder bump is formed. The partially connection body is cooled. The cooled partially connection body is heated to a temperature equal to or higher than the melting point of the solder bump in a reducing atmosphere, thereby to form a permanent connection body by melting the partially connection body while removing an oxide film existing on a surface of the partially connection body.Type: ApplicationFiled: September 15, 2010Publication date: March 31, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hideo Aoki, Masatoshi Fukuda, Kanako Sawada, Yasuhiro Koshio
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Publication number: 20100320258Abstract: In one embodiment, a first substrate having first solder bumps and a second substrate having second solder bumps are stacked while temporarily tacking the solder bumps to each other, and then a stack is disposed inside a furnace. The gas in the furnace is exhausted to be in a reduced pressure atmosphere, and then a carboxylic acid gas is introduced into the furnace. While increasing a temperature inside the furnace where the carboxylic acid gas is introduced, the gas in the furnace is exhausted to be in a reduced pressure atmosphere at a temperature in a range from a reduction temperature of oxide films by the carboxylic acid gas to lower than a melting temperature of the solder bumps. By increasing the temperature inside the furnace up to a temperature in a range of the melting temperature of the solder bumps and higher, the first solder bumps and the second solder bumps are melted and joined.Type: ApplicationFiled: June 15, 2010Publication date: December 23, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kanako Sawada, Hideo Aoki, Naoyuki Komuta, Koji Ogiso
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Patent number: 7045886Abstract: A semiconductor device is disclosed which has a first substrate with wiring formed thereon, a second substrate mounted above the first substrate with a conductive plug buried in the second substrate to penetrate between upper and lower surfaces thereof, a plurality of semiconductor chips mounted above the second substrate and having a terminal electrode as electrically connected to the first substrate through the conductive plug of the second substrate, and a resin buried in an empty space or gap between adjacent ones of the plurality of semiconductor chips.Type: GrantFiled: February 28, 2003Date of Patent: May 16, 2006Assignee: Kabushiki Kaisha ToshibaInventor: Kanako Sawada
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Publication number: 20050266668Abstract: A semiconductor device comprises a semiconductor element having first electrode pads and solder bumps, and a substrate having second electrode pads connected to the first electrode pads via the solder bumps. The semiconductor element has an insulating film with a low dielectric constant. The group of the solder bumps is provided with a solder bump in which a stress intensity factor K in a notch shape formed by the first electrode pad and the outline of the solder bump, when looking at a cross section through the center of the first electrode pad and the solder bump, is such that on the chip edge side it is less than or equal to its value on the chip center side. Thereby, cracking or delamination of the semiconductor element due to the insulating film with a low dielectric constant can be restrained.Type: ApplicationFiled: May 26, 2005Publication date: December 1, 2005Inventors: Kanako Sawada, Toshitsune lijima, Soichi Homma
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Patent number: 6930382Abstract: A semiconductor device includes a first substrate including an element, a first plug penetrating through the first substrate, made of a conductive material, and electrically connected with the element, a second substrate provided above the first substrate, and electrically connected with the element via the first plug, and a second plug penetrating through the first substrate, made of a non-dielectric material, and being not electrically connected with the second substrate.Type: GrantFiled: June 25, 2004Date of Patent: August 16, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Kanako Sawada, Keiichi Sasaki
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Publication number: 20050006786Abstract: A semiconductor device is disclosed which has a first substrate with wiring formed thereon, a second substrate mounted above the first substrate with a conductive plug buried in the second substrate to penetrate between upper and lower surfaces thereof, a plurality of semiconductor chips mounted above the second substrate and having a terminal electrode as electrically connected to the first substrate through the conductive plug of the second substrate, and a resin buried in an empty space or gap between adjacent ones of the plurality of semiconductor chips.Type: ApplicationFiled: August 11, 2004Publication date: January 13, 2005Applicant: Kabushiki Kaisha ToshibaInventor: Kanako Sawada
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Patent number: 6841469Abstract: A semiconductor device comprises a first substrate including an element, a first plug penetrating through the first substrate, made of a conductive material, and electrically connected with the element, a second substrate provided above the first substrate, and electrically connected with the element via the first plug, and a second plug penetrating through the first substrate, made of a non-dielectric material, and being not electrically connected with the second substrate.Type: GrantFiled: December 26, 2002Date of Patent: January 11, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Kanako Sawada, Keiichi Sasaki
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Publication number: 20040235234Abstract: A semiconductor device comprises a first substrate including an element, a first plug penetrating through the first substrate, made of a conductive material, and electrically connected with the element, a second substrate provided above the first substrate, and electrically connected with the element via the first plug, and a second plug penetrating through the first substrate, made of a non-dielectric material, and being not electrically connected with the second substrate.Type: ApplicationFiled: June 25, 2004Publication date: November 25, 2004Applicant: Kabushiki Kaisha ToshibaInventors: Kanako Sawada, Keiichi Sasaki
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Publication number: 20030222350Abstract: A semiconductor device is disclosed which has a first substrate with wiring formed thereon, a second substrate mounted above the first substrate with a conductive plug buried in the second substrate to penetrate between upper and lower surfaces thereof, a plurality of semiconductor chips mounted above the second substrate and having a terminal electrode as electrically connected to the first substrate through the conductive plug of the second substrate, and a resin buried in an empty space or gap between adjacent ones of the plurality of semiconductor chips.Type: ApplicationFiled: February 28, 2003Publication date: December 4, 2003Inventor: Kanako Sawada
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Publication number: 20030168744Abstract: A semiconductor device comprises a first substrate including an element, a first plug penetrating through the first substrate, made of a conductive material, and electrically connected with the element, a second substrate provided above the first substrate, and electrically connected with the element via the first plug, and a second plug penetrating through the first substrate, made of a non-dielectric material, and being not electrically connected with the second substrate.Type: ApplicationFiled: December 26, 2002Publication date: September 11, 2003Inventors: Kanako Sawada, Keiichi Sasaki
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Patent number: 6087715Abstract: To provide a highly reliable semiconductor device which does not suffer from a crack in its package, a semiconductor chip 12 is mounted on a lead frame 11 with a bonding layer 13 between them, and they are sealed with a sealing resin 14. The lead frame 11 has a base member 11a essentially consisting of Cu and an oxide film 11b essentially consisting of an oxide of the base member 11a formed on the base member and having a thickness of about 50 nm or below. By controlling the oxide film 11b to a thickness of about 50 nm or below, an adhesion strength with the sealing resin 14 is improved greatly, so that a package crack does not occur even if a large thermal load is applied in a reflow process for mounting.Type: GrantFiled: June 21, 1999Date of Patent: July 11, 2000Assignees: Kabushiki Kaisha Toshiba, Anam Industrial Co., Ltd.Inventors: Kanako Sawada, Hee Yeoul Yoo, Atsushi Kurosu, Kenji Takahashi
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Patent number: 5937279Abstract: To provide a highly reliable semiconductor device which does not suffer from a crack in its package, a semiconductor chip 12 is mounted on a lead frame 11 with a bonding layer 13 between them, and they are sealed with a sealing resin 14. The lead frame 11 has a base member 11a essentially consisting of Cu and an oxide film 11b essentially consisting of an oxide of the base member 11a formed on the base member and having a thickness of about 50 nm or below. By controlling the oxide film 11b to a thickness of about 50 nm or below, an adhesion strength with the sealing resin 14 is improved greatly, so that a package crack does not occur even if a large thermal load is applied in a reflow process for mounting.Type: GrantFiled: April 21, 1998Date of Patent: August 10, 1999Assignees: Kabushiki Kaisha Toshiba, Anam Industrial Co., Ltd.Inventors: Kanako Sawada, Hee Yeoul Yoo, Atsushi Kurosu, Kenji Takahashi
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Patent number: 5424250Abstract: A method for manufacturing a semiconductor device in which two resin encapsulating sheets, each having a convex portion, are brought into contact with a semiconductor chip. The semiconductor chip is then encapsulated by pressing the chip between the encapsulating sheets.Type: GrantFiled: March 22, 1994Date of Patent: June 13, 1995Assignee: Kabushiki Kaisha ToshibaInventor: Kanako Sawada