Patents by Inventor Kaname Ebihara

Kaname Ebihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device package and semiconductor device
    Patent number: 11581246
    Abstract: A semiconductor device package is disclosed. The package according to one example includes a base having a main surface made of a metal, a dielectric side wall having a bottom surface facing the main surface, a joining material containing silver (Ag) and joining the main surface of the base and the bottom surface of the side wall to each other, a lead made of a metal joined to an upper surface of the side wall on a side opposite to the bottom surface, and a conductive layer not containing silver (Ag). The conductive layer is provided between the bottom surface and the upper surface of the side wall at a position overlapping the lead when viewed from a normal direction of the main surface. The conductive layer is electrically connected to the joining material, extends along the bottom surface, and is exposed from a lateral surface of the side wall.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: February 14, 2023
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Shingo Inoue, Kaname Ebihara
  • SEMICONDUCTOR DEVICE PACKAGE AND SEMICONDUCTOR DEVICE
    Publication number: 20220005751
    Abstract: A semiconductor device package is disclosed. The package according to one example includes a base having a main surface made of a metal, a dielectric side wall having a bottom surface facing the main surface, a joining material containing silver (Ag) and joining the main surface of the base and the bottom surface of the side wall to each other, a lead made of a metal joined to an upper surface of the side wall on a side opposite to the bottom surface, and a conductive layer not containing silver (Ag). The conductive layer is provided between the bottom surface and the upper surface of the side wall at a position overlapping the lead when viewed from a normal direction of the main surface. The conductive layer is electrically connected to the joining material, extends along the bottom surface, and is exposed from a lateral surface of the side wall.
    Type: Application
    Filed: February 13, 2020
    Publication date: January 6, 2022
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Shingo INOUE, Kaname EBIHARA
  • Doherty amplifier and semiconductor device
    Patent number: 8598954
    Abstract: A Doherty amplifier includes a carrier amplifier including a first FET, the first FET having a plurality of gate electrodes, and a peaking amplifier including a second FET, the second FET having a plurality of gate electrodes, a gate-to-gate interval of the gate electrodes of the second FET being shorter than a gate-to-gate interval of the first FET.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: December 3, 2013
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventors: Hiroaki Deguchi, Kaname Ebihara
  • Doherty amplifier and semiconductor device
    Patent number: 8395450
    Abstract: A Doherty amplifier includes a carrier amplifier including a first FET, the first FET having a plurality of gate electrodes, and a peaking amplifier including a second FET, the second FET having a plurality of gate electrodes, a gate-to-gate interval of the gate electrodes of the second FET being shorter than a gate-to-gate interval of the first FET.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: March 12, 2013
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventors: Hiroaki Deguchi, Kaname Ebihara
  • DOHERTY AMPLIFIER AND SEMICONDUCTOR DEVICE
    Publication number: 20120019326
    Abstract: A Doherty amplifier includes a carrier amplifier including a first FET, the first FET having a plurality of gate electrodes, and a peaking amplifier including a second FET, the second FET having a plurality of gate electrodes, a gate-to-gate interval of the gate electrodes of the second FET being shorter than a gate-to-gate interval of the first FET.
    Type: Application
    Filed: July 19, 2011
    Publication date: January 26, 2012
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Hiroaki Deguchi, Kaname Ebihara