Patents by Inventor Kaname Ozawa
Kaname Ozawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160154924Abstract: A semiconductor design method is disclosed. Bumps are assigned to multiple Input and Output (I/O) sections of a chip. A plane is formed by deploying vias at locations of the bumps which are allocated to I/O sections of power supplies and grounds, with respect to a package on which the chip is mounted. An allocation of the bumps is changed with respect to the I/O sections of the power supplies and the grounds among the multiple I/O sections based on a number of the vias inside a void formed on the plane.Type: ApplicationFiled: November 30, 2015Publication date: June 2, 2016Inventor: Kaname Ozawa
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Patent number: 8097954Abstract: A semiconductor device of the invention includes a substrate in which a power-supply electrode and a ground electrode are provided. A first semiconductor chip is disposed over the substrate and has a first conductor layer formed on a surface facing a second semiconductor chip. A second conductor layer is disposed over the first semiconductor chip and has a second conductor layer formed on a surface facing the first semiconductor chip. And an adhesive layer is disposed between the first conductor layer and the second conductor layer and bonds together the first semiconductor chip and the second semiconductor chip. In the semiconductor device, the adhesive layer and the first and second conductor layers function as a capacitor.Type: GrantFiled: August 23, 2006Date of Patent: January 17, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Kaname Ozawa, Mitsutaka Sato, Yoshiyuki Yoneda
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Patent number: 7251801Abstract: A method of design of a circuit board enabling high density conductor lines to be drawn efficiently. A rats nest is formed by connecting pads to which terminals of an electronic device are connected and external connection terminals by lines. A region with the highest density of lines of the rats nest is then selected and design rules relating to routes and dimensions of conductor lines are set in the region with the highest density of lines of the rats nest. Conductor lines are then laid at the region with the highest density of lines of the rats nest, and whether or not the conductor lines can be laid at the region with the highest density of lines of the rats nest is confirmed. Setting of the design rules and laying of conductor lines are if the conductor lines cannot be laid, and the conductor lines of the remaining regions are laid by the set design rules if the conductor lines can be laid.Type: GrantFiled: December 23, 2004Date of Patent: July 31, 2007Assignee: Fujitsu LimitedInventors: Kaname Ozawa, Mitsutaka Sato, Tetsuya Fujisawa, Yoshiyuki Yoneda, Ryuji Nomoto, Yoshitaka Aiba
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Publication number: 20070138616Abstract: A semiconductor device, includes a supporting board; and a semiconductor element mounted on a first main surface of the supporting board. The supporting board includes a first electrode formed on the first main surface, a second electrode formed on a second main surface, and an opening or notch forming part. A first electrode pad of the semiconductor element faces and is connected to the first electrode of the supporting board. A second electrode pad of the semiconductor element and the second electrode of the supporting board are electrically connected via the opening or notch forming part.Type: ApplicationFiled: February 8, 2007Publication date: June 21, 2007Applicant: FUJITSU LIMITEDInventors: Tetsuya Fujisawa, Kaname Ozawa, Mitsutaka Sato
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Publication number: 20070001298Abstract: A semiconductor device of the invention includes a substrate in which a power-supply electrode and a ground electrode are provided. A first semiconductor chip is disposed over the substrate and has a first conductor layer formed on a surface facing a second semiconductor chip. A second conductor layer is disposed over the first semiconductor chip and has a second conductor layer formed on a surface facing the first semiconductor chip. And an adhesive layer is disposed between the first conductor layer and the second conductor layer and bonds together the first semiconductor chip and the second semiconductor chip. In the semiconductor device, the adhesive layer and the first and second conductor layers function as a capacitor.Type: ApplicationFiled: August 23, 2006Publication date: January 4, 2007Applicant: FUJITSU LIMITEDInventors: Kaname Ozawa, Mitsutaka Sato, Yoshiyuki Yoneda
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Patent number: 7138723Abstract: A semiconductor chip is secured in a state deformed into a substantially cylinder shape by a coating material formed on its surface. The deformed semiconductor chip is flip-chip connected to an interposer and sealed with sealing resin onto the interposer. Solder balls are provided, as external terminals, on the other side of the interposer.Type: GrantFiled: December 8, 2004Date of Patent: November 21, 2006Assignee: Fujitsu LimitedInventors: Kazuyuki Aiba, Akira Takashima, Kaname Ozawa, Tetsuya Hiraoka, Takaaki Suzuki, Yasurou Matsuzaki
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Publication number: 20060040532Abstract: A method of design of a circuit board enabling high density conductor lines to be drawn efficiently. A rats nest is formed by connecting pads to which terminals of an electronic device are connected and external connection terminals by lines. A region with the highest density of lines of the rats nest is then selected and design rules relating to routes and dimensions of conductor lines are set in the region with the highest density of lines of the rats nest. Conductor lines are then laid at the region with the highest density of lines of the rats nest, and whether or not the conductor lines can be laid at the region with the highest density of lines of the rats nest is confirmed. Setting of the design rules and laying of conductor lines are if the conductor lines cannot be laid, and the conductor lines of the remaining regions are laid by the set design rules if the conductor lines can be laid.Type: ApplicationFiled: December 23, 2004Publication date: February 23, 2006Applicant: FUJITSU LIMITEDInventors: Kaname Ozawa, Mitsutaka Sato, Tetsuya Fujisawa, Yoshiyuki Yoneda, Ryuji Nomoto, Yoshitaka Aiba
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Publication number: 20050082684Abstract: A semiconductor chip is secured in a state deformed into a substantially cylinder shape by a coating material formed on its surface. The deformed semiconductor chip is flip-chip connected to an interposer and sealed with sealing resin onto the interposer. Solder balls are provided, as external terminals, on the other side of the interposer.Type: ApplicationFiled: December 8, 2004Publication date: April 21, 2005Applicant: FUJITSU LIMITEDInventors: Kazuyuki Aiba, Akira Takashima, Kaname Ozawa, Tetsuya Hiraoka, Takaaki Suzuki, Yasurou Matsuzaki
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Patent number: 6777799Abstract: In a stacked semiconductor device which has a plurality of semiconductor chips of desired sizes stacked as one package, a first semiconductor chip is mounted on a flexible printed wiring board provided with external connecting terminals. A printed circuit board is placed and mounted on the first semiconductor chip by flip-chip bonding. A second semiconductor chip is secured onto the printed circuit board. The second semiconductor chip is connected to the flexible printed wiring board by wire bonding. The first semiconductor chip is connected to the flexible printed wiring board by wire bonding via the printed circuit board.Type: GrantFiled: July 22, 2003Date of Patent: August 17, 2004Assignee: Fujitsu LimitedInventors: Katsuhito Kikuma, Mitsutaka Ikeda, Yoshihiro Tsukidate, Yuji Akashi, Kaname Ozawa, Akira Takashima, Takao Nishimura
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Publication number: 20040051119Abstract: In a stacked semiconductor device which has a plurality of semiconductor chips of desired sizes stacked as one package, a first semiconductor chip is mounted on a flexible printed wiring board provided with external connecting terminals. A printed circuit board is placed and mounted on the first semiconductor chip by flip-chip bonding. A second semiconductor chip is secured onto the printed circuit board. The second semiconductor chip is connected to the flexible printed wiring board by wire bonding. The first semiconductor chip is connected to the flexible printed wiring board by wire bonding via the printed circuit board.Type: ApplicationFiled: July 22, 2003Publication date: March 18, 2004Applicant: FUJITSU LIMITEDInventors: Katsuhito Kikuma, Mitsutaka Ikeda, Yoshihiro Tsukidate, Yuji Akashi, Kaname Ozawa, Akira Takashima, Takao Nishimura
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Patent number: 6621169Abstract: In a stacked semiconductor device which has a plurality of semiconductor chips of desired sizes stacked as one package, a first semiconductor chip is mounted on a flexible printed wiring board provided with external connecting terminals. A printed circuit board is placed and mounted on the first semiconductor chip by flip-chip bonding. A second semiconductor chip is secured onto the printed circuit board. The second semiconductor chip is connected to the flexible printed wiring board by wire bonding. The first semiconductor chip is connected to the flexible printed wiring board by wire bonding via the printed circuit board.Type: GrantFiled: August 29, 2001Date of Patent: September 16, 2003Assignee: Fujitsu LimitedInventors: Katsuhito Kikuma, Mitsutaka Ikeda, Yoshihiro Tsukidate, Yuji Akashi, Kaname Ozawa, Akira Takashima, Tadashi Uno, Takao Nishimura, Fumihiko Ando, Hiroshi Onodera, Hayato Okuda
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Publication number: 20020027295Abstract: In a stacked semiconductor device which has a plurality of semiconductor chips of desired sizes stacked as one package, a first semiconductor chip is mounted on a flexible printed wiring board provided with external connecting terminals. A printed circuit board is placed and mounted on the first semiconductor chip by flip-chip bonding. A second semiconductor chip is secured onto the printed circuit board. The second semiconductor chip is connected to the flexible printed wiring board by wire bonding. The first semiconductor chip is connected to the flexible printed wiring board by wire bonding via the printed circuit board.Type: ApplicationFiled: August 29, 2001Publication date: March 7, 2002Applicant: Fujitsu LimitedInventors: Katsuhito Kikuma, Mitsutaka Ikeda, Yoshihiro Tsukidate, Yuji Akashi, Kaname Ozawa, Akira Takashima, Tadashi Uno, Takao Nishimura, Fumihiko Ando, Hiroshi Onodera, Hayato Okuda
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Patent number: 6316838Abstract: A semiconductor device includes a substrate provided with a plurality of leads, a face-down semiconductor element provided on one surface of the substrate, a first stacked semiconductor element and a second stacked semiconductor element provided on another surface of the substrate and connected to the substrate by wires, and an extended wiring mechanism for connecting electrodes of the face-down semiconductor element and electrodes of the first and second semiconductor elements. The connected electrodes are equi-electrodes whose electrical characteristics are equal.Type: GrantFiled: March 20, 2000Date of Patent: November 13, 2001Assignee: Fujitsu LimitedInventors: Kaname Ozawa, Hayato Okuda, Tetsuya Hiraoka, Mitsutaka Sato, Yuji Akashi, Akira Okada, Masahiko Harayama
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Patent number: 6215182Abstract: A semiconductor device includes the first through third semiconductor devices which are stacked on a substrate and the first through third wires for connecting the semiconductor elements and the substrate. The first wires serve to connect electrodes of the first semiconductor element positioned uppermost and electrodes of the second semiconductor element. The second wires serve to connect the electrodes of the second semiconductor element and electrodes of the third semiconductor element. The third wires serve to connect the electrodes of the third semiconductor element and bonding pads of the substrate. Between the first wires and the electrodes of the second semiconductor element and between the second wires and the electrodes of the third semiconductor element, stud bumps are provided so as to form space therebetween, thereby avoiding short-circuits therebetween.Type: GrantFiled: March 20, 2000Date of Patent: April 10, 2001Assignee: Fujitsu LimitedInventors: Kaname Ozawa, Hayato Okuda, Ryuji Nomoto, Yuji Akashi, Katsuro Hiraiwa