Patents by Inventor Kanehide Kenmizaki
Kanehide Kenmizaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6633508Abstract: Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.Type: GrantFiled: August 28, 2001Date of Patent: October 14, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Masaya Muranaka, Shinichi Miyatake, Yukihide Suzuki, Kanehide Kenmizaki, Makoto Morino, Tetsuya Kitame
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Publication number: 20020031036Abstract: Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.Type: ApplicationFiled: August 28, 2001Publication date: March 14, 2002Inventors: Masaya Muranaka, Shinichi Miyatake, Yukihide Suzuki, Kanehide Kenmizaki, Makoto Morino, Tetsuya Kitame
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Patent number: 6282141Abstract: Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.Type: GrantFiled: May 15, 2000Date of Patent: August 28, 2001Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Masaya Muranaka, Shinichi Miyatake, Yukihide Suzuki, Kanehide Kenmizaki, Makoto Morino, Tetsuya Kitame
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Patent number: 6064605Abstract: Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.Type: GrantFiled: September 14, 1999Date of Patent: May 16, 2000Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Masaya Muranaka, Shinichi Miyatake, Yukihide Suzuki, Kanehide Kenmizaki, Makoto Morino, Tetsuya Kitame
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Patent number: 5969996Abstract: Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.Type: GrantFiled: August 31, 1998Date of Patent: October 19, 1999Assignee: Hiachi, Ltd.Inventors: Masaya Muranaka, Shinichi Miyatake, Yukihide Suzuki, Kanehide Kenmizaki, Makoto Morino, Tetsuya Kitame
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Patent number: 5818784Abstract: Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.Type: GrantFiled: April 26, 1996Date of Patent: October 6, 1998Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Masaya Muranaka, Shinichi Miyatake, Yukihide Suzuki, Kanehide Kenmizaki, Makoto Morino, Tetsuya Kitame
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Patent number: 5761149Abstract: A dynamic RAM is provided with a main word lines; a plurality of subsidiary word lines which are arranged in the direction of bit lines crossing the main word line and to which a plurality of dynamic memory cells are connected; a plurality of subsidiary word selection lines which are extended so as to perpendicularly intersect the main word line and through which a selection signal for selecting one of the plurality of subsidiary word lines is transmitted; and a logic circuit for receiving a selection signal from the main word line and a selection signal from each of the subsidiary word selection lines to thereby form a selection signal for selecting one of the subsidiary word lines. In the dynamic RAM, the voltage level of each of the main word line and the subsidiary word selection lines is made to be equal to the ground potential when the line is in a not-selected state.Type: GrantFiled: July 12, 1996Date of Patent: June 2, 1998Assignees: Hitachi, Ltd., Texas Instruments Inc.Inventors: Yukihide Suzuki, Kanehide Kenmizaki, Tsugio Takahashi, Masayuki Nakamura, Makoto Saeki, Chisa Makimura, Katsuo Komatsuzaki, Shunichi Sukegawa
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Patent number: 5598373Abstract: A defect remedy LSI mounted on a memory module, comprising: an input interface portion for capturing address and control signals, the input interface portion being the same as that of a dynamic RAM; an input/output interface portion corresponding to a data bus of a memory device comprised of a plurality of dynamic random access memories; a memory circuit to which a chip address and an X defective address of any of the plurality of random access memories are electrically written, the memory circuit being substantially made nonvolatile; a redundancy remedy RAM portion composed of a static RAM wherein a word line is selected by a compare match signal between an X address signal and the defective address of the memory circuit, the X address signal and the defective address being captured via the input interface portion, and a column is selected by a Y address signal captured via the input interface portion; a selecting portion for connecting a data input/output bus of the redundancy remedy RAM portion to an inputType: GrantFiled: June 7, 1995Date of Patent: January 28, 1997Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Shoji Wada, Kanehide Kenmizaki, Masaya Muranaka, Masahiro Ogata, Hidetomo Aoyagi, Tetsuya Kitame, Masahiro Katayama, Shoji Kubono, Yukihide Suzuki, Makoto Morino, Sinichi Miyatake, Seiichi Shundo, Yoshihisa Koyama, Nobuhiko Ohno
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Patent number: 5467315Abstract: The semiconductor memory is facilitated with control circuitry for effecting plural self-refresh modes having respectively different refresh periods. The plural self-refresh modes are typified by a PS (pseudo) refresh mode which is applied when the memory is in the nonselected state for a comparatively long period of time, such as in the state in which memory backup is being facilitated, and by a VS (virtual) refresh mode in which the refreshing operation of the memory cells is effected intermittently during the intervals of memory accessings. The pseudo refresh mode has a longer refresh time period than the virtual refresh mode. The control circuitry also has counter circuits for the generating of refresh address signals in accordance with a first timing signal indicative of a pseudo refresh mode and a second timing signal indicative of a virtual refresh mode, the latter timing signal being a higher frequency signal.Type: GrantFiled: April 28, 1994Date of Patent: November 14, 1995Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Takeshi Kajimoto, Yutaka Shimbo, Katsuyuki Sato, Masahiro Ogata, Kanehide Kenmizaki, Shouji Kubono, Nobuo Kato, Kiichi Manita, Michitaro Kanamitsu
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Patent number: 5311476Abstract: There is provided in connection with a semiconductor memory, such as of the pseudostatic RAM, a layout of the circuit components thereof including a method of testing the memory. There is provided an oscillation circuit which is capable of withstanding bumping of the power source voltage (varying) which effects stabilization regarding the operation of the circuits included therewith including a refresh timer circuit. There is also provided for testing a refresh timer circuit and a semiconductor memory which includes a refresh timer circuit. There is further provided for an output buffer which is capable of high speed operation with respect to memory data readout, a voltage generating circuit which is capable of stable operation and a fuse circuit, such as provided in connection with redundant circuitry in the memory and which is characterized as having a configuration of a fuse logic gate circuit employing complementary channel MOSFETs together with a fuse.Type: GrantFiled: June 18, 1992Date of Patent: May 10, 1994Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Takeshi Kajimoto, Yutaka Shimbo, Katsuyuki Sato, Masahiro Ogata, Kanehide Kenmizaki, Shouji Kubono, Nobuo Kato, Kiichi Manita, Michitaro Kanamitsu
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Patent number: 5161120Abstract: A data output buffer is provided in connection with a semiconductor memory, such as a pseudostatic RAM, which is capable of high speed operation with respect to memory data readout. The buffer includes a latch circuit comprising a pair of NAND gate circuits having input and output terminals connected in cross connection, a pair of precharge MOSFETs provided respectively between the noninverted and inverted input terminals of the latch circuit, a pair of CMOS NAND gates which transfer the inverted signal of the latch circuit according to an inverted timing signal and a pair of series-connected MOSFETs effecting a pull-up/pull-down arrangement which receives the inverted signal of the output signal of the NAND gates.Type: GrantFiled: March 20, 1990Date of Patent: November 3, 1992Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Takeshi Kajimoto, Yutaka Shimbo, Katsuyuki Sato, Masahiro Ogata, Kanehide Kenmizaki, Shouji Kubono, Nobuo Kato, Kiichi Manita, Michitaro Kanamitsu
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Patent number: 4849939Abstract: A semiconductor memory having a memory array, a first and a second selection line which are connected to a memory cell, and a selection means which selects either one of the selection lines. The selection means includes a selection circuit which optionally selects the first selection line or the second selection line when an address signal corresponding to the first selection line is aligned with a predetermined address signal.Type: GrantFiled: September 24, 1987Date of Patent: July 18, 1989Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Masaya Muranaka, Hiromi Matsuura, Kanehide Kenmizaki, Osamu Okayama