Abstract: In a semiconductor IC device, a first IC chip having a plurality of first electrodes and a second IC chip having a plurality of second electrodes are stacked. A plurality of relay electrodes are provided on the first IC chip. The first electrodes are electrically connected to a lead frame via respective first conductive wires. One end of each of the relay electrodes is electrically connected to the respective second electrodes via respective second conductive wires and the other end of each of the relay electrodes is connected the lead frame via third conductive wires. No one of the second conductive wires crosses another one of the other second conductive wires and no one of the third conductive wires crosses another one of the third second conductive wires.

Abstract: In a semiconductor IC device, a first IC chip having a plurality of first electrodes and a second IC chip having a plurality of second electrodes are stacked. A plurality of relay electrodes are provided on the first IC chip. The first electrodes are electrically connected to a lead frame via respective first conductive wires. One end of each of the relay electrodes is electrically connected to the respective second electrodes via respective second conductive wires and the other end of each of the relay electrodes is connected the lead frame via third conductive wires. No one of the second conductive wires crosses another one of the other second conductive wires and no one of the third conductive wires crosses another one of the third second conductive wires.

Abstract: A buffer circuit according to the present invention includes an input terminal for inputting an input signal, an inverter circuit for inverting the input signal and outputting the inverted input signal to an output terminal, wherein the inverter circuit has a plurality of PMOS transistors and a plurality of NMOS transistors; each of the plurality of PMOS transistors has a source connected to a power source, a drain connected to the output terminal, and a gate connected to the input terminal; each of the plurality of NMOS transistors has a source connected to a ground, a drain connected to the output terminal, and a gate connected to the input terminal; and the gate of at least one of the plurality of PMOS transistors and NMOS transistors is connected to the input terminal via a fuse element which can be selectively disconnected.