Abstract: Dishing is known to be a problem after CMP of dielectric layers in which the distribution of embedded metal is non-uniform. This problem has been solved by populating those areas where the density of embedded metal is low with unconnected regions that, instead of being uniformly filled with metal, are made up of metallic patterns whose combined area within a given region is about half the total area of the region itself. Two examples of such patterns are a line stripe pattern (similar to a parquet flooring tile) and a checker board pattern. Data is presented comparing the parasitic capacitances resulting from the use of patterns of this type relative to conventional solid patterns. The effect of aligning the regions so as to reduce their degree of overlap with wiring channels is also discussed.

Abstract: A semiconductor structure prevents energy that is used to blow a fuse from causing damage. The semiconductor structure includes a device, guard ring, and at least one protection layer. The device is constructed on the semiconductor substrate underneath the fuse. The seal ring, which surrounds the fuse, is constructed on at least one metal layer between the device and the fuse for confining the energy therein. The protection layer is formed within the seal ring, on at least one metal layer between the device and the fuse for shielding the device from being directly exposed to the energy.

Abstract: A laser fuse structure for a semiconductor device, the laser fuse structure having an array of laser fuses wherein one or more of the fuses in the array have a tortuous fuse line extending between first and second connectors that connect the fuse to an underlying circuit area.

Abstract: A method of integrated circuit fabrication includes first forming at least one via in an insulting layer, and thereafter forming at least one trench-like structure separately. After a via is formed in an insulating layer, a layer of resist material is formed on the surface of the insulting layer and substantially filled the via. This step is followed by patterning at least one trench-like structure on the resist layer, and the trench-like structure is etched to the desired level. In some other embodiments, at least one trench-like structure is formed before at least one via is formed. An integrated circuit is manufactured by the aforementioned methods.

Abstract: In accordance with the objective of the invention a new method is provided for the creation of a seal ring having dissimilar elements. The Critical Dimensions of the seal ring are selected with respect to the CD of other device features, such a seal vias, such that the difference in etch sensitivity between the created seal ring and the via holes is removed. All etch of the simultaneously etched features is completed at the same time, avoiding punch through of an underlying layer of etch stop material.

Abstract: A semiconductor package seal ring including a plurality of insulating layers, a plurality of conductive runners each embedded in one of the insulating layers, and a plurality of conductive posts each contacting one of the conductive runners and extending through at least one of the insulating layers and at least partially through an opening in another one of the conductive runners.

Abstract: A semiconductor package seal ring including a plurality of insulating layers, a plurality of conductive runners each embedded in one of the insulating layers, and a plurality of conductive posts each contacting one of the conductive runners and extending through at least one of the insulating layers and at least partially through an opening in another one of the conductive runners.

Abstract: A multiple layer metal interconnect process provides for both good electrical properties and good mechanical properties by using a first extremely low k dielectric material at the lower level metal layers, a second extremely low k dielectric material at the middle level metal layers, and a low k dielectric material at the upper level metal layers.

Abstract: A method of integrated circuit fabrication includes first forming at least one via in an insulting layer, and thereafter forming at least one trench-like structure separately. After a via is formed in an insulating layer, a layer of resist material is formed on the surface of the insulting layer and substantially filled the via. This step is followed by patterning at least one trench-like structure on the resist layer, and the trench-like structure is etched to the desired level. In some other embodiments, at least one trench-like structure is formed before at least one via is formed. An integrated circuit is manufactured by the aforementioned methods.

Abstract: A method of fabrication used for semiconductor integrated circuit devices to define a thin copper fuse at a top via opening, in a partial etch, dual damascene integration scheme, efficiently reducing top metal thickness in a fusible link, for the purpose of laser ablation. Some advantages of the method are: (a) avoids copper fuse contact to low dielectric material, which is subject to the thermal shock of laser ablation, (b) increases insulating material thickness over the fuse using better thickness control, and most importantly, (c) reduces the copper fuse thickness, for easy laser ablation of the copper fuse, and finally, (d) uses USG, undoped silicate glass to avoid direct contact with low dielectric constant materials.

Abstract: An improved dual damascene structure, and process for manufacturing it, are described in which the via hole is first lined with a layer of silicon nitride prior to adding the diffusion barrier and copper. This allows use of a barrier layer that is thinner than normal (since the silicon nitride liner is an effective diffusion barrier) so that more copper may be included in the via hole, resulting in an improved conductance of the via. A key feature of the process that is used to make the structure is the careful control of the etching process. In particular, the relative selectivity of the etch between silicon oxide and silicon nitride must be carefully adjusted.

Abstract: The present invention discloses a method for forming metal silicide on an electronic structure by first depositing a metal layer on top of a silicon layer of polysilicon, single crystal silicon or amorphous silicon capable of forming a metal silicide, and then irradiating the metal layer with laser energy for a sufficient length of time such that a layer of metal silicide is formed at the metal interface with polysilicon, single crystal silicon and amorphous silicon. The unreacted metal layer on the metal silicide is then removed by a wet dipping method by selecting a suitable etchant for the metal. The present invention novel method can be applied to various metallic materials such as Ti, Co, W, Pt, Hf, Ta, Mo, Pd and Cr. The laser source utilized is a pulse Excimer laser of XeCl, ArF or XeF.

Abstract: An improved dual damascene structure, and process for manufacturing it, are described in which the via hole is first lined with a layer of silicon nitride prior to adding the diffusion barrier and copper. This allows use of a barrier layer that is thinner than normal (since the silicon nitride liner is an effective diffusion barrier) so that more copper may be included in the via hole, resulting in an improved conductance of the via. A key feature of the process that is used to make the structure is the careful control of the etching process. In particular, the relative selectivity of the etch between silicon oxide and silicon nitride must be carefully adjusted.

Abstract: A process for creating a metal filled, dual damascene opening, in a composite insulator layer, has been developed. The process features selective RIE procedures, used to create a wide diameter opening in an upper silicon oxide layer, and a narrow diameter opening in a lower silicon oxide layer. Small area, silicon nitride islands, or shapes, a component of the composite insulator layer, are used as a stop layer, during the selective RIE procedures. The use of small area, silicon nitride shapes, offers less composite insulator capacitance, than counterparts fabricated using larger area, silicon nitride stop layers.

Abstract: The present invention includes patterning a metal layer on a glass substrate. A dielectric layer is formed on the metal layer. An amorphous silicon layer is subsequently formed on the dielectric layer. A first positive photoresist is formed on the amorphous silicon layer. Then, a back-side exposure is used by using the gate electrodes as a mask. A bake step is performed to expand the lower portion of the photoresist. Next, a second positive photoresist layer is formed on the amorphous silicon layer and the residual first positive photoresist layer. A further back-side exposure is employed again from the back side of the substrate using the gate electrode as the mask. A second back step is applied to expand the lower portion of the second positive photoresist layer. An ion implantation is performed by using the second positive photoresist as a mask. Next, the substrate is then annealed. Amorphous silicon layer is then patterned.

Abstract: The present invention includes forming a conductive layer on a substrate. Portions of the conductive layer are removed using a first photoresist layer as a mask. A first oxide layer is formed over the conductive layer and the substrate, and an amorphous silicon layer is then formed on the first oxide layer. After annealing the amorphous silicon layer, thereby transforming amorphous silicon layer to a polysilicon layer, a second oxide layer is formed on the polysilicon layer. The second oxide layer is removed using a second photoresist layer as a mask. An amorphous silicon carbon layer is formed over the second oxide layer and the polysilicon layer, and a heavily-doped amorphous silicon carbon layer is formed on the amorphous silicon carbon layer.

Abstract: The present invention discloses a hybrid polysilicon/amorphous silicon TFT device for switching a LCD and a method for fabrication wherein a n.sup.+ doped amorphous silicon layer is advantageously used as a mask during a laser annealing process such that only a selected portion of a hydrogenated amorphous silicon layer is converted to a crystalline structure while other portions retain their amorphous structure. As a result, a polysilicon TFT and at least one amorphous silicon TFT are formed in the same structure and the benefits of both a polysilicon TFT and amorphous silicon TFT such as a high charge current and a low leakage current are retained in the hybrid structure.

Abstract: The present invention discloses a hybrid polysilicon/amorphous silicon TFT device for switching a LCD and a method for fabrication wherein a n.sup.+ doped amorphous silicon layer is advantageously used as a mask during a laser annealing process such that only a selected portion of a hydrogenated amorphous silicon layer is converted to a crystalline structure while other portions retain their amorphous structure. As a result, a polysilicon TFT and at least one amorphous silicon TFT are formed in the same structure and the benefits of both a polysilicon TFT and amorphous silicon TFT such as a high charge current and a low leakage current are retained in the hybrid structure.

Abstract: Method for forming a polycrystalline silicon (ploy-Si) film of a semiconductor device includes forming the gate electrode on a substrate and depositing a dielectric layer on the substrate and the conductive layer. Then a first layer (microcrystalline silicon:.mu.c-Si) is formed on the dielectric layer and a second layer (hydrogenated amorphous silicon:a-Si:H) is deposited on the first layer. Noted that the polycrystalline silicon (poly-Si) can be fabricated by applying the laser annealing to the first layer and the second layer to transform them to poly-Si. Annealing the first layer and the second layer by laser, followed by fabricating the source and drain electrodes, thus the TFT with good electrical characteristics is fabricated.

Abstract: The present invention includes forming a conductive layer on a substrate. Portions of the conductive layer are removed using a first photoresist layer as a mask. A first oxide layer is formed over the conductive layer and the substrate, and an amorphous silicon layer is then formed on the first oxide layer. After annealing the amorphous silicon layer, thereby transforming amorphous silicon layer to a polysilicon layer, a second oxide layer is formed on the polysilicon layer. The second oxide layer is removed using a second photoresist layer as a mask. An amorphous silicon carbon layer is formed over the second oxide layer and the polysilicon layer, and a heavily-doped amorphous silicon carbon layer is formed on the amorphous silicon carbon layer.