Patents by Inventor Kang-Cheng Lin

Kang-Cheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040198035
    Abstract: A method of integrated circuit fabrication includes first forming at least one via in an insulting layer, and thereafter forming at least one trench-like structure separately. After a via is formed in an insulating layer, a layer of resist material is formed on the surface of the insulting layer and substantially filled the via. This step is followed by patterning at least one trench-like structure on the resist layer, and the trench-like structure is etched to the desired level. In some other embodiments, at least one trench-like structure is formed before at least one via is formed. An integrated circuit is manufactured by the aforementioned methods.
    Type: Application
    Filed: April 3, 2003
    Publication date: October 7, 2004
    Inventors: Chao-Cheng Chen, Kang-Cheng Lin
  • Patent number: 6737345
    Abstract: A method of fabrication used for semiconductor integrated circuit devices to define a thin copper fuse at a top via opening, in a partial etch, dual damascene integration scheme, efficiently reducing top metal thickness in a fusible link, for the purpose of laser ablation. Some advantages of the method are: (a) avoids copper fuse contact to low dielectric material, which is subject to the thermal shock of laser ablation, (b) increases insulating material thickness over the fuse using better thickness control, and most importantly, (c) reduces the copper fuse thickness, for easy laser ablation of the copper fuse, and finally, (d) uses USG, undoped silicate glass to avoid direct contact with low dielectric constant materials.
    Type: Grant
    Filed: September 10, 2002
    Date of Patent: May 18, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Kang-Cheng Lin, Chin-Chiu Hsia
  • Patent number: 6348733
    Abstract: An improved dual damascene structure, and process for manufacturing it, are described in which the via hole is first lined with a layer of silicon nitride prior to adding the diffusion barrier and copper. This allows use of a barrier layer that is thinner than normal (since the silicon nitride liner is an effective diffusion barrier) so that more copper may be included in the via hole, resulting in an improved conductance of the via. A key feature of the process that is used to make the structure is the careful control of the etching process. In particular, the relative selectivity of the etch between silicon oxide and silicon nitride must be carefully adjusted.
    Type: Grant
    Filed: September 5, 2000
    Date of Patent: February 19, 2002
    Assignee: Industrial Technology Research Institute
    Inventor: Kang-Cheng Lin
  • Patent number: 6316357
    Abstract: The present invention discloses a method for forming metal silicide on an electronic structure by first depositing a metal layer on top of a silicon layer of polysilicon, single crystal silicon or amorphous silicon capable of forming a metal silicide, and then irradiating the metal layer with laser energy for a sufficient length of time such that a layer of metal silicide is formed at the metal interface with polysilicon, single crystal silicon and amorphous silicon. The unreacted metal layer on the metal silicide is then removed by a wet dipping method by selecting a suitable etchant for the metal. The present invention novel method can be applied to various metallic materials such as Ti, Co, W, Pt, Hf, Ta, Mo, Pd and Cr. The laser source utilized is a pulse Excimer laser of XeCl, ArF or XeF.
    Type: Grant
    Filed: October 8, 1997
    Date of Patent: November 13, 2001
    Assignee: Industrial Technology Research Institute
    Inventors: Kang-Cheng Lin, Hong-Woei Wu
  • Patent number: 6140220
    Abstract: An improved dual damascene structure, and process for manufacturing it, are described in which the via hole is first lined with a layer of silicon nitride prior to adding the diffusion barrier and copper. This allows use of a barrier layer that is thinner than normal (since the silicon nitride liner is an effective diffusion barrier) so that more copper may be included in the via hole, resulting in an improved conductance of the via. A key feature of the process that is used to make the structure is the careful control of the etching process. In particular, the relative selectivity of the etch between silicon oxide and silicon nitride must be carefully adjusted.
    Type: Grant
    Filed: July 8, 1999
    Date of Patent: October 31, 2000
    Assignee: Industrial Technology Institute Reseach
    Inventor: Kang-Cheng Lin
  • Patent number: 6093632
    Abstract: A process for creating a metal filled, dual damascene opening, in a composite insulator layer, has been developed. The process features selective RIE procedures, used to create a wide diameter opening in an upper silicon oxide layer, and a narrow diameter opening in a lower silicon oxide layer. Small area, silicon nitride islands, or shapes, a component of the composite insulator layer, are used as a stop layer, during the selective RIE procedures. The use of small area, silicon nitride shapes, offers less composite insulator capacitance, than counterparts fabricated using larger area, silicon nitride stop layers.
    Type: Grant
    Filed: December 7, 1998
    Date of Patent: July 25, 2000
    Assignee: Industrial Technology Research Institute
    Inventor: Kang-Cheng Lin
  • Patent number: 6063653
    Abstract: The present invention includes patterning a metal layer on a glass substrate. A dielectric layer is formed on the metal layer. An amorphous silicon layer is subsequently formed on the dielectric layer. A first positive photoresist is formed on the amorphous silicon layer. Then, a back-side exposure is used by using the gate electrodes as a mask. A bake step is performed to expand the lower portion of the photoresist. Next, a second positive photoresist layer is formed on the amorphous silicon layer and the residual first positive photoresist layer. A further back-side exposure is employed again from the back side of the substrate using the gate electrode as the mask. A second back step is applied to expand the lower portion of the second positive photoresist layer. An ion implantation is performed by using the second positive photoresist as a mask. Next, the substrate is then annealed. Amorphous silicon layer is then patterned.
    Type: Grant
    Filed: July 7, 1998
    Date of Patent: May 16, 2000
    Assignee: Industrial Technology Research Institute
    Inventors: Kang-Cheng Lin, Gwo-Long Lin
  • Patent number: 6018166
    Abstract: The present invention includes forming a conductive layer on a substrate. Portions of the conductive layer are removed using a first photoresist layer as a mask. A first oxide layer is formed over the conductive layer and the substrate, and an amorphous silicon layer is then formed on the first oxide layer. After annealing the amorphous silicon layer, thereby transforming amorphous silicon layer to a polysilicon layer, a second oxide layer is formed on the polysilicon layer. The second oxide layer is removed using a second photoresist layer as a mask. An amorphous silicon carbon layer is formed over the second oxide layer and the polysilicon layer, and a heavily-doped amorphous silicon carbon layer is formed on the amorphous silicon carbon layer.
    Type: Grant
    Filed: July 30, 1998
    Date of Patent: January 25, 2000
    Assignee: Industrial Technology Research Institute
    Inventors: Kang-Cheng Lin, Hong-Jye Hong
  • Patent number: 5920772
    Abstract: The present invention discloses a hybrid polysilicon/amorphous silicon TFT device for switching a LCD and a method for fabrication wherein a n.sup.+ doped amorphous silicon layer is advantageously used as a mask during a laser annealing process such that only a selected portion of a hydrogenated amorphous silicon layer is converted to a crystalline structure while other portions retain their amorphous structure. As a result, a polysilicon TFT and at least one amorphous silicon TFT are formed in the same structure and the benefits of both a polysilicon TFT and amorphous silicon TFT such as a high charge current and a low leakage current are retained in the hybrid structure.
    Type: Grant
    Filed: June 27, 1997
    Date of Patent: July 6, 1999
    Assignee: Industrial Technology Research Institute
    Inventor: Kang-Cheng Lin
  • Patent number: 5864150
    Abstract: The present invention discloses a hybrid polysilicon/amorphous silicon TFT device for switching a LCD and a method for fabrication wherein a n.sup.+ doped amorphous silicon layer is advantageously used as a mask during a laser annealing process such that only a selected portion of a hydrogenated amorphous silicon layer is converted to a crystalline structure while other portions retain their amorphous structure. As a result, a polysilicon TFT and at least one amorphous silicon TFT are formed in the same structure and the benefits of both a polysilicon TFT and amorphous silicon TFT such as a high charge current and a low leakage current are retained in the hybrid structure.
    Type: Grant
    Filed: May 21, 1998
    Date of Patent: January 26, 1999
    Assignee: Industrial Technology Research Institute
    Inventor: Kang-Cheng Lin
  • Patent number: 5834071
    Abstract: Method for forming a polycrystalline silicon (ploy-Si) film of a semiconductor device includes forming the gate electrode on a substrate and depositing a dielectric layer on the substrate and the conductive layer. Then a first layer (microcrystalline silicon:.mu.c-Si) is formed on the dielectric layer and a second layer (hydrogenated amorphous silicon:a-Si:H) is deposited on the first layer. Noted that the polycrystalline silicon (poly-Si) can be fabricated by applying the laser annealing to the first layer and the second layer to transform them to poly-Si. Annealing the first layer and the second layer by laser, followed by fabricating the source and drain electrodes, thus the TFT with good electrical characteristics is fabricated.
    Type: Grant
    Filed: February 11, 1997
    Date of Patent: November 10, 1998
    Assignee: Industrial Technology Research Institute
    Inventor: Kang-Cheng Lin
  • Patent number: 5811325
    Abstract: The present invention includes forming a conductive layer on a substrate. Portions of the conductive layer are removed using a first photoresist layer as a mask. A first oxide layer is formed over the conductive layer and the substrate, and an amorphous silicon layer is then formed on the first oxide layer. After annealing the amorphous silicon layer, thereby transforming amorphous silicon layer to a polysilicon layer, a second oxide layer is formed on the polysilicon layer. The second oxide layer is removed using a second photoresist layer as a mask. An amorphous silicon carbon layer is formed over the second oxide layer and the polysilicon layer, and a heavily-doped amorphous silicon carbon layer is formed on the amorphous silicon carbon layer.
    Type: Grant
    Filed: December 31, 1996
    Date of Patent: September 22, 1998
    Assignee: Industrial Technology Research Institute
    Inventors: Kang-Cheng Lin, Hong-Jye Hong
  • Patent number: 5783843
    Abstract: A method of fabricating a polycrystalline silicon thin-film transistor having two symmetrical lateral resistors is disclosed. Two sub-gates are formed along with a gate in the gate metal or polysilicon layer of the thin-film transistor. The two sub-gates that are located symmetrically on the two sides of the gate have equal distances to the gate. One sub-gate is near the drain of the thin film transistor and the other near the source. Two sections in the polycrystalline silicon layer of the thin film transistor are blocked by the two sub-gates and no impurity material is doped. The two undoped sections form the symmetrical lateral resistors of this invention. The lateral resistor near the drain decreases the electric field in the nearby depletion area when the thin-film transistor is switched off. The current leakage is reduced.
    Type: Grant
    Filed: March 21, 1997
    Date of Patent: July 21, 1998
    Assignee: Industrial Technology Research Institute
    Inventor: Kang-Cheng Lin
  • Patent number: 5658808
    Abstract: A method of fabricating a polycrystalline silicon thin-film transistor having two symmetrical lateral resistors is disclosed. Two sub-gates are formed along with a gate in the gate metal or polysilicon layer of the thin-film transistor. The two sub-gates that are located symmetrically on the two sides of the gate have equal distances to the gate. One sub-gate is near the drain of the thin film transistor and the other near the source. Two sections in the polycrystalline silicon layer of the thin film transistor are blocked by the two sub-gates and no impurity material is doped. The two undoped sections form the symmetrical lateral resistors of this invention. The lateral resistor near the drain decreases the electric field in the nearby depletion area when the thin-film transistor is switched off. The current leakage is reduced.
    Type: Grant
    Filed: August 14, 1996
    Date of Patent: August 19, 1997
    Assignee: Industrial Technology Research Institute
    Inventor: Kang-Cheng Lin