Abstract: Methods of operating a charge trap nonvolatile memory device include operations to erase a first string of nonvolatile memory cells by selectively erasing even-numbered nonvolatile memory cells in the first string and then selectively erasing the odd-numbered nonvolatile memory cells in the first string, which may be interleaved with the even-numbered nonvolatile memory cells. This operation to selectively erase the even-numbered nonvolatile memory cells may include erasing the even-numbered nonvolatile memory cells while simultaneously biasing the odd-numbered nonvolatile memory cells in a blocking condition that inhibits erasure of the odd-numbered nonvolatile memory cells. The operation to selectively erase the odd-numbered nonvolatile memory cells may include erasing the odd-numbered nonvolatile memory cells while simultaneously biasing the even-numbered nonvolatile memory cells in a blocking condition that inhibits erasure of the even-numbered nonvolatile memory cells.

Abstract: Methods of operating a charge trap nonvolatile memory device include operations to erase a first string of nonvolatile memory cells by selectively erasing a first plurality of nonvolatile memory cells in the first string and then selectively erasing a second plurality of nonvolatile memory cells in the first string, which may be interleaved with the first plurality of nonvolatile memory cells. This operation to selectively erase the first plurality of nonvolatile memory cells may include erasing the first plurality of nonvolatile memory cells while simultaneously biasing the second plurality of nonvolatile memory cells in a blocking condition that inhibits erasure of the second plurality of nonvolatile memory cells.

Abstract: Methods of operating a charge trap nonvolatile memory device include operations to erase a first string of nonvolatile memory cells by selectively erasing a first plurality of nonvolatile memory cells in the first string and then selectively erasing a second plurality of nonvolatile memory cells in the first string, which may be interleaved with the first plurality of nonvolatile memory cells. This operation to selectively erase the first plurality of nonvolatile memory cells may include erasing the first plurality of nonvolatile memory cells while simultaneously biasing the second plurality of nonvolatile memory cells in a blocking condition that inhibits erasure of the second plurality of nonvolatile memory cells.

Abstract: Disclosed is a flash memory device and a program verification method thereof which can prevent a misjudgment as to whether flash memory cells are programmed or not. The flash memory device includes: a program verification voltage generator for variably generating program verification voltages used to verify whether the flash memory cells are programmed or not and a word line level selector for transferring the program verification voltages to word lines connected to control gates of the flash memory cells. The flash memory cells that are verified as uncertain as to whether the flash memory cells are programmed or not can be completely programmed since the program verification operation is carried out with program verification voltage levels that are changed according to the selective activations of the program verification control signals.

Abstract: A NAND flash memory device is provided. The memory device includes M input/output pins for inputting and outputting M-bit data (M is any natural number), first and second input buffer circuits, an address register, a command register, and a data input register. The first and second input buffer circuits receive N least significant bits (N is any natural number) and N most significant bits, respectively, of the M-bit data inputted via the input/output pins. The address register receives as an address an output of the first input buffer circuit in response to address load signals. The command register receives as a command an output of the first address buffer circuit in response to the command load signal. The data input register simultaneously receives outputs of the first and second input buffer circuits in response to the data load signal, as data to be programmed. The M-bit data latched in the data input register is loaded on the sense and latch block via a data bus.

Abstract: Disclosed is a flash memory device and a program verification method thereof which can prevent a misjudgment as to whether flash memory cells are programmed or not. The flash memory device includes: a program verification voltage generator for variably generating program verification voltages used to verify whether the flash memory cells are programmed or not and a word line level selector for transferring the program verification voltages to word lines connected to control gates of the flash memory cells. The flash memory cells that are verified as uncertain as to whether the flash memory cells are programmed or not can be completely programmed since the program verification operation is carried out with program verification voltage levels that are changed according to the selective activations of the program verification control signals.

Abstract: A NAND flash memory device is provided. The memory device includes M input/output pins for inputting and outputting M-bit data (M is any natural number), first and second input buffer circuits, an address register, a command register, and a data input register. The first and second input buffer circuits receive N least significant bits (N is any natural number) and N most significant bits, respectively, of the M-bit data inputted via the input/output pins. The address register receives as an address an output of the first input buffer circuit in response to address load signals. The command register receives as a command an output of the first address buffer circuit in response to the command load signal. The data input register simultaneously receives outputs of the first and second input buffer circuits in response to the data load signal, as data to be programmed. The M-bit data latched in the data input register is loaded on the sense and latch block via a data bus.

Abstract: The well regions of pumping units of charge pump circuits are maintained electrically floating. By maintaining the wells electrically floating, reduced impact from the body effect may be obtained. More specifically, integrated circuit charge pump circuits boost a first voltage from a voltage source to a second voltage at an output terminal. The charge pump circuits include a plurality of pumping units in an integrated circuit substrate of first conductivity type, that are serially connected between the voltage source and the output terminal. Each of the pumping units includes a well region of second conductivity type in the integrated circuit substrate of first conductivity type. The well region of second conductivity type is electrically floating.

Abstract: A semiconductor memory includes a plurality of main bit lines led to sense amplifiers and arranged in a row, direction, a first group of sub bit lines interposed between the memory banks and connected to the main bit lines through a first group of selection transistors, and a second group of sub bit lines interposed between the memory banks and the first group of sub bit lines and connected to a common ground line through a second group of selection transistors.

Abstract: A sense amplifier for transferring data between a data input/output line and a bit line in a nonvolatile semiconductor memory device includes two isolated current paths to prevent data collisions. A transistor transfers a bit of input data from the data input/output line to a first terminal of a two-terminal latch in response to a load control signal. The second terminal of the latch is connected to the bit line. A second transistor transfers a bit of output data from the second terminal of the latch to the data input/output line in response to a read control signal. While the bit of input data is being transferred, the second transistor isolates the second terminal of the latch from the data input/output line.

Abstract: A non-volatile integrated circuit memory device includes an array of memory cells. Each of a plurality of word lines corresponds to a respective row of memory cells, and each of a plurality of bit lines corresponds to a respective column of the memory cells. A current supplying transistor includes a source coupled to a supply voltage source, a gate coupled to a static voltage source, and a drain coupled to the bit lines. The current supplying transistor provides a static current to the bit lines during data read operations. A storage unit has a pair of latches coupled to respective input/output lines to perform a data exchange. The latches are further coupled to respective bit lines to perform a sense operation during the data read operation.

Abstract: The present invention provides an electrically erasable and programmable nonvolatile semiconductor memory device (EEPROM) with NAND structured cells which is capable of reducing the number of peripheral circuits required to drive each memory block. The EEPROM according to the present invention includes memory blocks having transfer transistors controlled by a memory block selection signal, wherein the transfer transistors serve as a path through which control gate driving signals are supplied, and wherein control gate driving signals are applied to word lines at full voltage due to a self-boosting operation of each transfer transistor.

Abstract: The present invention provides an electrically erasable and programmable nonvolatile semiconductor memory device (EEPROM) with NAND structured cells which is capable of reducing the number of peripheral circuits required to drive each memory block. The EEPROM according to the present invention includes memory blocks having transfer transistors controlled by a memory block selection signal, wherein the transfer transistors serve as a path through which control gate driving signals are supplied, and wherein control gate driving signals are applied to word lines at full voltage due to a self-boosting operation of each transfer transistor.

Abstract: The present invention provides an electrically erasable and programmable nonvolatile semiconductor memory device (EEPROM) with NAND structured cells which is capable of reducing the number of peripheral circuits required to drive each memory block. The EEPROM according to the present invention includes memory blocks having transfer transistors controlled by a memory block selection signal, wherein the transfer transistors serve as a path through which control gate driving signals are supplied, and wherein control gate driving signals are applied to word lines at full voltage due to a self-boosting operation of each transfer transistor.

Abstract: The present invention discloses a non-volatile memory device having a multi-level gate structure. The storage cell transistor in the cell array region and the transistor in the peripheral circuit region have the same multi-level gate structure. Also, multi-level polycrystalline silicon layers in the peripheral circuit region are connected to each other, and thus utilized as an electrically singular gate electrode. The gate structures of the two regions are formed through a single etching process, so that the decreased processing number of photolithography simplifies overall process, and reduces the damage on the field oxide layer to thereby enhance an insulating performance.

Abstract: A mask ROM having a defect repairing function stores address signals corresponding to a defective memory cell and then, selectively activates either a redundancy row decoder or a row decoder according to whether the address signals stored are identical to address signals supplied externally. The mask ROM includes first and second memory cell arrays formed by grouping in a word line direction a plurality of read only memory cells arranged in rows and columns; first and second row decoders for combining row address signals supplied externally so as to selectively drive the word lines of the first and second memory cell arrays; and a row decoder selector for storing therein address signals according to a row block including a defective memory cell, of the first memory cell array so as to inactivate the first row decoder and activate the second row decoder when the external row address signals are equal to the address signals stored in the row decoder selector.

Abstract: A device for achieving optimum erasure of the memory cells of a NAND type flash EEPROM. A memory string comprises a bit line, word lines and cell transistors with the gates respectively connected to the word lines and the channels cascaded between the bit line and ground voltage. A high voltage supplying device is connected between the bit line and the memory string for generating a first high voltage. A bit line selection transistor has the channel connected between the high voltage supplying device and the memory string and the gate connected to a bit line selection signal. In a first erasing operation, an erasing voltage applying device applies a first voltage to the gate of the bit line selection transistor and an erasing voltage to the gates of the cell transistors.

Abstract: A nonvolatile semiconductor memory device particularly relates to an EEPROM having NAND-structured cells, and an optimizing programming method thereof. The device includes a memory cell array arranged as matrix having NAND cells formed by a plurality of serially-connected memory cells each of which is formed by stacking a charge storage layer and a control gate on a semiconductor substrate, and enables electrical erasing by the mutual exchange of a charge between the charge storage layer and the substrate, a data latch circuit, a high voltage supply circuit, a current source circuit, a program checking circuit, and a program status detecting circuit. The programming state is optimized while being unaffected by the variance of process parameters, over-programming is prevented by the use of a verifying potential, and the performance of the chip is enhanced by automatically optimizing the programming with a chip's internal verification function.