Abstract: A nonvolatile semiconductor memory having a single bit cell array and a multi-bit cell array formed on a substrate of the memory is provided. The memory includes a plurality of memory blocks that correspond to the input/output lines and is divided into a plurality of pages. A plurality of bit lines of the single bit cell array is coupled to a plurality of page buffers. The multi-bit cell array includes a plurality of memory blocks in which one of the blocks corresponds to a plurality of the input/output lines and is divided into a plurality of pages. A plurality of bit lines of the multi-bit cell array is coupled to a plurality of page buffers, A timing controller arranges the processing operations in the two arrays.