Abstract: A device may include a processor that may recover the signals misallocated in the deblending process of seismic data acquired with simultaneous sources. The processor may update the primary signal estimate based at least in part on a separation operation that separates coherence signals from noise signals in an output associated with the residual determined to be remaining energy for separation. The processor may be incorporated into the iterative primary signal estimate of the deblending process or be applied towards preexisting deblending output. In response to satisfying an end condition, the processor may transmit a deblended output that includes the weak coherence signals recovered from the misallocation or error in the primary signal estimate. The processor may also transmit the deblended output for use in generating a seismic image. The seismic image may represent hydrocarbons in a subsurface region of Earth or subsurface drilling hazards.

Abstract: An integrated circuit includes a specific pin, an output circuit, a voltage detector, and a controller. The output circuit is coupled to the specific pin. The voltage detector obtains a detection voltage value from the specific pin. In response to an alert request, the controller provides a control signal to the output circuit based on the detection voltage value, so as to selectively control the output circuit to transmit the alert signal to the specific pin. When the control signal instructs the integrated circuit to operate in a blocking mode, the output circuit blocks the alert signal from being transmitted to the specific pin. When the control signal instructs the integrated circuit to operate in a transmission mode, the output circuit transmits the alert signal to the specific pin.

Abstract: A semiconductor structure is provided. The semiconductor structure include a substrate and a first dielectric layer having at least one via over the substrate. The first dielectric layer includes a first portion having a first thickness and a second portion having a second thickness greater than the first thickness. The semiconductor structure further includes a second dielectric layer containing at least one first conductive line overlying the first portion of the first dielectric layer and at least one second conductive line overlying the second portion of the first dielectric layer. The at least one first conductive line includes a first conductive portion and a conductive cap, and the at least one second conductive line including a second conductive portion having a top surface coplanar with a top surface of the conductive cap.

Abstract: A method of forming a semiconductor structure includes removing a top portion of a conductive feature disposed in a first dielectric layer and over a semiconductor substrate to form a first recess, depositing a second dielectric layer over the first dielectric layer, where the second dielectric layer includes a first region disposed vertically above the first recess and a second region disposed adjacent the first region, and forming a third dielectric layer over the second dielectric layer. The method further includes subsequently forming openings in the third dielectric layer that extend to expose the second dielectric layer, depositing a conductive material in the openings, and planarizing the conductive material to form conductive features in the first and the second regions, where the planarizing completely removes portions of the third dielectric layer disposed in the second region.

Abstract: A method is provided. The method includes the following steps: obtaining a predetermined initial timing for signal transmission from user equipment (UE) to a satellite through a gateway in a non-terrestrial network; and in response to a number of failures of the signal transmission being greater than or equal to a first predetermined number, utilizing the UE to shift timing for a subsequent signal transmission using a timing-adjustment mechanism.

Abstract: The present disclosure provides a method for fabricating a semiconductor structure that includes a first dielectric layer over a semiconductor substrate, and a first cap layer over the first dielectric layer. The method includes forming a first metal feature in the first dielectric layer; performing a first CMP process on the first metal feature using a first rotation rate; and performing a second CMP process on the first metal feature using a second rotation rate slower than the first rotation rate. The second CMP process may be time-based. The second CMP process may stop on the first cap layer. After performing the second CMP process, the method includes removing the first cap layer. The first CMP process may have a first polishing rate to the first metal feature. The second CMP process may have a second polishing rate to the first metal feature lower than the first polishing rate.

Abstract: A method of forming a semiconductor structure includes removing a top portion of a conductive feature disposed in a first dielectric layer and over a semiconductor substrate to form a first recess, depositing a second dielectric layer over the first dielectric layer, where the second dielectric layer includes a first region disposed vertically above the first recess and a second region disposed adjacent the first region, and forming a third dielectric layer over the second dielectric layer. The method further includes subsequently forming openings in the third dielectric layer that extend to expose the second dielectric layer, depositing a conductive material in the openings, and planarizing the conductive material to form conductive features in the first and the second regions, where the planarizing completely removes portions of the third dielectric layer disposed in the second region.

Abstract: The present disclosure provides a method for forming semiconductor structures. The method includes providing a device having a substrate, a first dielectric layer over the substrate, and a first conductive feature over the first dielectric layer, the first conductive feature comprising a first metal, the first metal being a noble metal. The method also includes depositing a second dielectric layer over the first dielectric layer and covering at least sidewalls of the first conductive feature; etching the second dielectric layer to form a trench; and forming a second conductive feature in the trench. The second conductive feature comprises a second metal different from the first metal.

Abstract: In a method for manufacturing a semiconductor device, a dielectric layer is formed over a substrate. A first pattern and a second pattern are formed in the first interlayer dielectric layer. The first pattern has a width greater than a width of the second pattern. A first metal layer is formed in the first pattern and the second pattern. A second metal layer is formed in the first pattern. A planarization operation is performed on the first and second metal layers so that a first metal wiring by the first pattern and a second metal wiring by the second pattern are formed. A metal material of the first metal layer is different from a metal material of the second metal layer. The first metal wiring includes the first and second metal layers and the second metal wiring includes the first metal layer but does not include the second metal layer.

Abstract: A velocity model is generated based upon seismic waveforms via any seismic model building method, such as full waveform inversion or tomography. Data representative of a measurement of a physical attribute of an area surrounding a well is received and an attribute model is generated based upon the velocity model and the data. An image is rendered based upon the attribute model for use with seismic exploration above a region of a subsurface comprising a hydrocarbon reservoir and containing structural or stratigraphic features conducive to a presence, migration, or accumulation of hydrocarbons.

Abstract: A method of seismic exploration above a region of the subsurface containing structural or stratigraphic features conducive to the presence, migration, or accumulation of hydrocarbons comprises accessing at least a portion of a blended seismic source survey, separating the at least two interfering seismic source excitations using inversion separation, producing one or more source gathers based on the separating, and using the one or more source gathers to explore for hydrocarbons within said region of the subsurface. The blended source seismic survey contains at least two interfering seismic source excitations therein, and the seismic source excitations can be produced by seismic source types having different signatures or frequency characteristics.

Abstract: The present disclosure provides a method for fabricating a semiconductor structure that includes a first dielectric layer over a semiconductor substrate, and a first cap layer over the first dielectric layer. The method includes forming a first metal feature in the first dielectric layer; performing a first CMP process on the first metal feature using a first rotation rate; and performing a second CMP process on the first metal feature using a second rotation rate slower than the first rotation rate. The second CMP process may be time-based. The second CMP process may stop on the first cap layer. After performing the second CMP process, the method includes removing the first cap layer. The first CMP process may have a first polishing rate to the first metal feature. The second CMP process may have a second polishing rate to the first metal feature lower than the first polishing rate.

Abstract: A User Equipment (UE) including a wireless transceiver and a controller is provided. The wireless transceiver performs wireless transmission and reception to and from a first service network utilizing a first RAT or a second service network utilizing a second RAT. The controller sends an indicator of a connection release request to the first service network via the wireless transceiver in response to terminating a first communication service with the first service network or in response to leaving the first service network for the second service network. Also, the controller releases a Radio Resource Control (RRC) connection with the first service network after sending the indicator of the connection release request.

Abstract: A semiconductor device is provided. The semiconductor device includes a dielectric layer over a substrate and a contact structure embedded in the dielectric layer. The contact structure includes a diffusion barrier contacting the dielectric layer, the diffusion barrier including a titanium (Ti)-containing alloy. The contact structure further includes a liner on the diffusion barrier, the liner including a noble metal. The contact structure further includes a conductive plug on the liner.

Abstract: Techniques for processing of seismic data. A seismic data set is received, wherein the seismic data set comprises a first data subset associated with a first seismic source and a second data subset associated with a second seismic source. An input is received indicating that a distance between the first seismic source and the second seismic source is greater than or equal to a threshold value. The second data set is filtered from the seismic data set to remove the second data subset from seismic data set to generate a filtered seismic data set in response to receiving the input and a coherence volume is generated based on the filtered seismic data set.

Abstract: An integrated circuit includes a specific pin, an output circuit, a voltage detector, and a controller. The output circuit is coupled to the specific pin. The voltage detector obtains a detection voltage value from the specific pin. In response to an alert request, the controller provides a control signal to the output circuit based on the detection voltage value, so as to selectively control the output circuit to transmit the alert signal to the specific pin. When the control signal instructs the integrated circuit to operate in a blocking mode, the output circuit blocks the alert signal from being transmitted to the specific pin. When the control signal instructs the integrated circuit to operate in a transmission mode, the output circuit transmits the alert signal to the specific pin.

Abstract: A user reading statistic data set relating to a natural language document is received. The user reading statistic data set includes information indicative of at least one of a set of user reading statistic types. A set of machine logic rules is applied to the user reading statistic data set to generate, as reading assistance to the reader with reading the natural language document, a user reading comprehension data set including information indicative of reading comprehension with respect to content of the natural language document.

Abstract: A method includes forming a first metal into a first trench in a dielectric layer, performing a thermal treatment to the first metal such that an average grain size of the first metal is increased, and performing a first chemical mechanical polish (CMP) process to the first metal after the performing the thermal treatment.

Abstract: Various examples and schemes pertaining to enhanced cell selection mechanisms in mobile communications are described. A user equipment (UE) performs a cell selection or reselection procedure to select a cell of a wireless network and establishes a wireless connection with the selected cell. In performing the cell selection or reselection procedure, the UE determines a frequency band and a subcarrier spacing (SCS) configuration by checking a profile, and the UE performs the cell selection or reselection procedure in the frequency band based on the SCS configuration.

Abstract: A method of forming a semiconductor structure includes removing a top portion of a conductive feature disposed in a first dielectric layer and over a semiconductor substrate to form a first recess, depositing a second dielectric layer over the first dielectric layer, where the second dielectric layer includes a first region disposed vertically above the first recess and a second region disposed adjacent the first region, and forming a third dielectric layer over the second dielectric layer. The method further includes subsequently forming openings in the third dielectric layer that extend to expose the second dielectric layer, depositing a conductive material in the openings, and planarizing the conductive material to form conductive features in the first and the second regions, where the planarizing completely removes portions of the third dielectric layer disposed in the second region.