Abstract: A field emission display, and method of making, including: a first substrate; a transparent electrode formed on the first substrate; a fluorescent layer of emitting light formed on a predetermined area of the transparent electrode; an insulating layer formed around the fluorescent layer on the other areas of the transparent electrode; a gate electrode formed on the insulating layer; a second substrate; a conductive cathode layer formed on the second substrate; and a tip for emitting electrons formed on the conductive cathode layer, the tip being aligned with the fluorescent layer in such a way that they may stand opposed to each other at a distance under a vacuum condition. The electrons are emitted from the tip of the fluorescent layer under control of the gate electrode. The tip is formed by taper-etching the tip layer in a RIE process. Subsequent evaporation of the tip to sharpen it is not necessary. This simplifies, and cuts the cost of, fabrication of the FED.

Abstract: A photodiode capable of obtaining a sufficient photo current/dark ratio at both a forward bias state and a reverse bias state. The photodiode includes a glass substrate, an aluminum film formed as a lower electrode over the glass substrate, an alumina film formed as a Schottky barrier over the aluminum film, a hydrogenated amorphous silicon film formed as a photo conduction layer over a portion of the alumina film, and a transparent conduction film formed as an upper electrode over the hydrogenated amorphous silicon film.

Abstract: A method of making thin film transistors, capable of reducing the extent of channel overlap between a gate electrode and source/drain regions, thereby achieving an improvement in signal-to-noise ratio. The method uses a impurity ion doping process and a process for forming a silicide layer using a refractory metal, so as to form source and drain electrodes in a self-aligned manner, with respect to the gate electrode. In order to avoid a channel overlap from occurring between the gate electrode and the source and drain electrodes, a photoresist pattern is subjected to a baking, which photoresist pattern defines an insulating layer pattern serving as a channel passivation layer to determine the of a channel region and the widths of source and drain regions. By the baking, the photoresist pattern flows outwardly so that its width is approximately equal to the length of the gate electrode.

Abstract: A slope etching process comprising the steps of coating a photoresist on a layer of hard material, baking the photoresist under a predetermined condition so that it flows down to have at its opposite side edges respective slant surface of a desired slope angle and then dry etching simultaneously the photoresist and the hard material layer so as to provide the hard material layer at its opposite side edges with a desired slope angle. In accordance with this process, the step coverage is improved, and thus the rate of poor products and the generation of noise are reduced.