Abstract: According to an embodiment, an electronic device may include a battery, a resonance circuit, a rectifier, a DC/DC converter, a charger, a switch, an overvoltage protection circuit configured to perform an overvoltage protection operation or to stop the overvoltage protection operation based on the voltage at the output terminal of the rectifier, a control circuit, and a communication circuit, and the control circuit may be configured to: based on a periodic repetition of a performance of the overvoltage protection operation and a stop of the overvoltage protection while the switch is in an off state, identify a first period during which the overvoltage protection operation is stopped, based on the first period, identify an expected voltage at an output terminal of the rectifier, to be expected, wherein the expected voltage is a voltage if the switch is in an on state, based on the expected voltage, identify whether an occurrence of an overvoltage is expected if the switch is in the on state, and control the c

Abstract: An electronic device includes a power transmitter; a first communication interface configured to support an Ultra-Wideband (UWB) communication scheme; a second communication interface configured to support a Bluetooth communication scheme; and a processor configured to: control the first communication interface to transmit a first signal and receive a second signal corresponding to the first signal via the first communication interface, identify, based on a difference between a transmission time of the first signal and a reception time of the second signal, first location information of a first external device, control the power transmitter to transmit a first driving power having a first magnitude, based on a first distance between the first external device and the electronic device being within a first range, the first distance being identified based on the first location information, establish a Bluetooth communication connection with the first external device, based on receiving, via the second communicat

Abstract: Provided is a processing device having improved reliability and power consumption efficiency of analog calculations as well as high cost efficiency due to reduction in a size of a bit-cell, and an electronic system including the processing device. The processing device includes: at least one bit-cell line on which a plurality of bit-cells are connected to each other in series, wherein each of the bit-cells includes: a first magnetic tunnel junction (MTJ) element; a second MTJ element connected to the first MTJ element in parallel; a first switching element connected to the first MTJ element in series; and a second switching element connected to the second MTJ element in series, and wherein on the bit-cell line, two adjacent bit-cells are connected to each other in series in a mirroring structure.

Abstract: Provided is a processing device having improved reliability and power consumption efficiency of analog calculations as well as high cost efficiency due to reduction in a size of a bit-cell, and an electronic system including the processing device. The processing device includes: at least one bit-cell line on which a plurality of bit-cells are connected to each other in series, wherein each of the bit-cells includes: a first magnetic tunnel junction (MTJ) element; a second MTJ element connected to the first MTJ element in parallel; a first switching element connected to the first MTJ element in series; and a second switching element connected to the second MTJ element in series, and wherein on the bit-cell line, two adjacent bit-cells are connected to each other in series in a mirroring structure.

Abstract: A magnetic memory device includes a plurality of first bit lines and a plurality of second bit lines, a plurality of first source lines respectively corresponding to the plurality of first bit lines and a plurality of second source lines respectively corresponding to the plurality of second bit lines, a plurality of first memory cells connected between the plurality of first bit lines and the plurality of first source lines, respectively, in a first region, the plurality of first memory cells respectively including a first memory device and a first selection transistor, and a plurality of second memory cells connected between the plurality of second bit lines and the plurality of second source lines, respectively, in a second region, the plurality of second memory cells respectively including a second memory device and a second selection transistor.

Abstract: Integrated circuits with magnetic random access memory (MRAM) devices and methods for fabricating such devices are provided. In an exemplary embodiment, a method for fabricating MRAM bitcells includes determining a desired inter-cell spacing between a first bitcell and a second bitcell and double patterning a semiconductor substrate to form semiconductor fin structures, wherein the semiconductor fin structures are formed in groups with an intra-group pitch between grouped semiconductor fin structures and with the inter-cell spacing between adjacent groups of semiconductor fin structures different from the intra-group pitch. The method further includes forming a first MRAM memory structure over the semiconductor fin structures in the first bitcell and forming a second MRAM memory structure over the semiconductor fin structures in the second bitcell. Also, the method includes forming a first source line for the first bitcell between the first MRAM memory structure and the second MRAM memory structure.

Abstract: A magnetic tunneling junction (MTJ) with a free layer that is less temperature sensitive and is reflow compatible at 260° C. The magnetic free layer may include various configurations, such as a single as-deposited crystalline magnetic layer or a composite free layer with more than one magnetic layers or a combination of composite and single magnetic layers. The layers of the composite magnetic free layer may include as-deposited crystalline magnetic free layers or a combination of as-deposited crystalline and as-deposited amorphous magnetic layers, with or without a spacer layer. An interface layer may be provided at an interface between the free layer and adjacent layer to apply tensile stress on the free layer in the direction perpendicular to the in-plane direction to enhance perpendicular magnetic anisotropy (PMA) of the free layer.

Abstract: Emerging memory chips and methods for forming an emerging memory chip are presented. For example, magnetic random access memory (MRAM) chip magnetic shielding and methods of forming a magnetic shield processed at the wafer-level are disclosed. The method includes providing a magnetic shield at the front side of the chip, back side of the chip, and also in the deep trenches surrounding or adjacent to magnetic tunnel junction (MTJ) array within the prime die region. Magnetic shield in the deep trenches connects front side and back side magnetic shield. This magnetic shielding method is applicable for both in-plane and perpendicular MRAM chips. The MTJ array is formed in the prime die region and in between adjacent inter layer dielectric (ILD) levels of the upper ILD layer in the back end of line (BEOL) of the MRAM chip.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, an integrated circuit includes a magnetic tunnel junction. The magnetic tunnel junction includes a fixed layer structure, a free layer structure, and a barrier layer disposed between the fixed layer structure and the free layer structure. The fixed layer structure includes a first magnetic layer and a second magnetic layer that is disposed between the first magnetic layer and the barrier layer. The first magnetic layer is configured to produce a first magnetic moment that substantially correlates to a second magnetic moment of the second magnetic layer as a function of temperature.

Abstract: Integrated circuits with magnetic random access memory (MRAM) devices and methods for fabricating such devices are provided. In an exemplary embodiment, a method for fabricating MRAM bitcells includes determining a desired inter-cell spacing between a first bitcell and a second bitcell and double patterning a semiconductor substrate to form semiconductor fin structures, wherein the semiconductor fin structures are formed in groups with an intra-group pitch between grouped semiconductor fin structures and with the inter-cell spacing between adjacent groups of semiconductor fin structures different from the intra-group pitch. The method further includes forming a first MRAM memory structure over the semiconductor fin structures in the first bitcell and forming a second MRAM memory structure over the semiconductor fin structures in the second bitcell. Also, the method includes forming a first source line for the first bitcell between the first MRAM memory structure and the second MRAM memory structure.

Abstract: A bottom pinned perpendicular magnetic tunnel junction (pMTJ) with high TMR which can withstand high temperature back-end-of-line (BEOL) processing is disclosed. The pMTJ includes a composite spacer layer between a SAF layer and a reference layer of the fixed magnetic layer of the pMTJ. The composite spacer layer includes a first non-magnetic (NM) spacer layer, a magnetic (M) spacer layer disposed over the first NM spacer layer and a second NM spacer layer disposed over the M layer. The M layer is a magnetically continuous amorphous layer, which provides a good template for the reference layer.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, an integrated circuit includes a magnetic tunnel junction. The magnetic tunnel junction includes a fixed layer structure, a free layer structure, and a barrier layer disposed between the fixed layer structure and the free layer structure. The fixed layer structure includes a first magnetic layer and a second magnetic layer that is disposed between the first magnetic layer and the barrier layer. The first magnetic layer is configured to produce a first magnetic moment that substantially correlates to a second magnetic moment of the second magnetic layer as a function of temperature.

Abstract: A method of forming a differential sensing STT MRAM design and the resulting device are provided. Embodiments include rows of programmable cells formed in a magnetoresistive random-access memory (MRAM) device, each row having a source line (SL); and rows of complimentary cells formed in the MRAM device, each row having a SL, wherein a SL of a row of programmable cells and a SL of a row of complimentary cells of a pair of rows form a merged SL.

Abstract: A method of forming a segmented FDSOI STT-MRAM using dummy WL blocks and the resulting device are provided. Embodiments include forming a plurality of FDSOI STT-MRAM active WL blocks laterally separated across a memory array; forming a FDSOI STT-MRAM dummy WL block parallel to and on opposite sides of each active WL block; forming a plurality of SL structures laterally separated across the memory array; forming a plurality of BL structures laterally separated across the memory array; and connecting the plurality of SL and BL structures to the plurality of active WL blocks.

Abstract: A material stack of a synthetic anti-ferromagnetic (SAF) reference layer of a perpendicular magnetic tunnel junction (MTJ) may include an SAF coupling layer. The material stack may also include and an amorphous spacer layer on the SAF coupling layer. The amorphous spacer layer may include an alloy or multilayer of tantalum and cobalt or tantalum and iron or cobalt and iron and tantalum. The amorphous spacer layer may also include a treated surface of the SAF coupling layer.

Abstract: A radiation detector and a method of operating the radiation detector. The radiation detector includes: a photoconductive layer between the array substrate and the counter electrode and having a particle-in-binder (PIB) structure in which a photoconductive particle and a binder are mixed; and an optical unit for providing light energy to the photoconductive layer to detrap a charge trapped in an interface between the photoconductive particle and the binder. The light energy includes ultraviolet rays and/or visible rays.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a magnetic tunnel junction with a fixed layer, a total free structure, and a barrier layer between the fixed layer and the total free structure. The total free structure includes a first free layer, a second free layer, and a first spacer layer disposed between the first and second free layers. The first spacer layer is non-magnetic. At least one of the first or second free layers include a primary free layer alloy with cobalt, iron, boron, and a free layer additional element. The free layer additional element is present at from about 1 to about 10 atomic percent. The free layer additional element is selected from one or more of molybdenum, aluminum, germanium, tungsten, vanadium, niobium, tantalum, zirconium, manganese, titanium, chromium, silicon, and hafnium.

Abstract: A magnetic tunneling junction (MTJ) with a reference layer is less temperature sensitive and is reflow compatible at 260° C. The reference layer may be a composite reference layer having n magnetic layers separated by (n?1) non-magnetic spacer layers. The reference layers may include low temperature coefficient reference layers or a combination of low temperature coefficient and high MR reference layers to produce a low temperature sensitive reference layer with good MR.

Abstract: A one time programming (OTP) apparatus unit cell includes magnetic tunnel junctions (MTJs) with reversed connections for placing the MTJ in an anti-parallel resistance state during programming. Increased MTJ resistance in its anti-parallel resistance state causes a higher programming voltage which reduces programming time and programming current.

Abstract: A magnetic tunneling junction (MTJ) with a free layer that is less temperature sensitive and is reflow compatible at 260° C. The magnetic free layer may include various configurations, such as a single as-deposited crystalline magnetic layer or a composite free layer with more than one magnetic layers or a combination of composite and single magnetic layers. The layers of the composite magnetic free layer may include as-deposited crystalline magnetic free layers or a combination of as-deposited crystalline and as-deposited amorphous magnetic layers, with or without a spacer layer. An interface layer may be provided at an interface between the free layer and adjacent layer to apply tensile stress on the free layer in the direction perpendicular to the in-plane direction to enhance perpendicular magnetic anisotropy (PMA) of the free layer.