Abstract: A communication method and apparatus are provided. The method includes: A first communication apparatus receives a first request, where the first request indicates the first communication apparatus to obtain information about a first tag. The first communication apparatus obtains the information about the first tag based on the first request, where the information about the first tag includes an identifier of the first tag. According to the method, after obtaining the information about the first tag, the first communication apparatus determines the corresponding first communication session for the information about the first tag, so that it can be ensured that the first communication apparatus can effectively and accurately transmit the information about the first tag by using the first communication session.

Abstract: An interconnection structure and a manufacturing method thereof are provided. The interconnection structure includes a first dielectric layer, a first conductive feature, a second dielectric layer, and a barrier layer. The first conductive feature is disposed on the first dielectric layer, the second dielectric layer is disposed on the first dielectric layer and surrounds the sidewalls of the first conductive feature, the barrier layer is disposed between the first dielectric layer and the second dielectric layer and between the sidewalls of the first conductive feature and the second dielectric layer.

Abstract: A display panel has functional component regions arranged along a first direction and a display region at least partially surrounding the functional component regions. The functional component regions include a first functional component region and a second functional component region. The display panel includes first signal lines located in the display region. One of the first signal lines has a least one part extending in the first direction, and the first signal lines are arranged in a second direction intersecting with the first direction. The first signal lines include a first-type signal line and a second-type signal line, and the first-type signal line includes at least two first-type connecting line. The second-type signal line includes a second-type connecting line.

Abstract: The semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a first dielectric layer, a first metal layer, a second metal layer, a first etching stop layer, a second etching stop layer, a second dielectric layer, a first via and a second via. The first metal layer and the second metal are embedded in the first dielectric layer. The first etching stop layer is disposed on the first dielectric layer. The second etching stop layer is disposed on the first etching stop layer. The second dielectric layer is disposed on the second etching stop layer. The first via and the second via are embedded in the second dielectric layer. A width of the second etching stop layer is smaller a width of the first etching stop layer.

Abstract: A display panel includes a display region, at least two functional component regions, first signal lines located in the display region, a first non-display region, a second non-display region, a first-type driving circuit located in the second non-display region, and second-type driving circuits located in the second non-display region. One of the first signal lines has a least one part extending in the first direction, and the first signal lines are arranged in a second direction intersecting with the first direction. The first signal lines include a first-type signal line and a second-type signal line, and the first-type signal line at least partially surrounds the functional component regions. In the first direction, at least one second-type signal line is broken at two sides of one of the functional component region.

Abstract: Semiconductor structures and methods of forming the same are provided. An exemplary method incudes forming a first dielectric layer over a first conductive feature, forming a conductive via extending through the first dielectric layer and coupled to the first conductive feature, forming a hard mask layer over the conductive via, patterning the hard mask layer to form a first opening exposing the first dielectric layer; forming a sacrificial layer to partially fill the first opening, forming a porous dielectric layer on the sacrificial layer, after the forming of the porous dielectric layer, selectively removing the sacrificial layer to form an air gap, forming a second dielectric layer over the porous dielectric layer, and replacing a portion of the patterned hard mask layer disposed directly over the conductive via with a second conductive feature.

Abstract: A display panel has functional component regions arranged along a first direction and a display region at least partially surrounding the functional component regions. The functional component regions include a first functional component region and a second functional component region that are arranged along a first direction. The display region located therebetween is provided with sub-pixels. The display panel includes first signal lines located in the display region. One of the first signal lines has a least one part extending in the first direction, and the first signal lines are arranged in a second direction intersecting with the first direction. The first signal lines include a first-type signal line and a second-type signal line, and the first-type signal line at least partially surrounds the functional component regions. In the first direction, at least one second-type signal line is broken at two sides of one of the functional component region.

Abstract: An interconnection structure includes a first dielectric layer, a first conductive feature, a first liner layer, a second conductive feature, a second liner layer, and an air gap. The first conductive feature is disposed in the first dielectric layer. The first liner layer is disposed between the first conductive feature and the first dielectric layer. The second conductive feature penetrates the first dielectric layer. The second liner layer is disposed between the second conductive feature and the first dielectric layer. The air gap is disposed in the first dielectric layer between the first liner layer and the second liner layer. The first liner layer and the second liner layer include metal oxide, metal nitride, or silicon oxide doped carbide.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first low dielectric constant (low-k) layer, a first metal layer, a metal cap layer, a dielectric on dielectric (DoD) layer, an etch stop layer (ESL), a second low-k layer, a metal via and a second metal layer. The dielectric constant of the first low-k layer is less than 4. The first metal layer is embodied in the first low-k layer. The first low-k layer exposes the first metal layer. The metal cap layer is disposed on the first metal layer. The DoD layer is disposed on the first low-k layer. The etch stop layer is disposed on the metal cap layer and the DoD layer. The second low-k layer is disposed above the etch stop layer. The metal via is embodied in the second low-k layer and connected to the first metal layer.

Abstract: The present disclosure relates to the field of display technology, and provides an optical module, a manufacturing method thereof, and a display device. The optical module includes: a substrate; a black matrix arranged on the substrate and a plurality of optical lenses spaced apart from each other, wherein an orthogonal projection of a gap between adjacent optical lenses onto the substrate is located within an orthogonal projection of the black matrix onto the substrate, and the black matrix is made of a ferrous metal oxide.

Abstract: A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.

Abstract: A method is provided for forming an integrated circuit (IC) chip package structure. The method includes: providing an interposer having a front surface and a back surface, the interposer comprising a substrate, at least one routing region, and at least one non-routing region; forming at least one warpage-reducing trench in the at least one non-routing region, wherein the at least one warpage-reducing trench extends from the front surface of the interposer to a first depth, the first depth smaller than a thickness between the front surface and the back surface of the interposer; depositing a warpage-relief material in the at least one warpage-reducing trench; and bonding the group of IC dies to the front surface of the interposer.

Abstract: A method includes forming a metal layer over a dielectric layer; forming hard masks over the metal layer; etching the metal layer using the hard masks as etch mask to form metal features; selectively forming dielectric liners on opposite sidewalls of each of the metal features, while leaving surfaces of the hard masks and the dielectric layer exposed by the dielectric liners; and forming an inter-metal dielectric layer laterally surrounding the metal features.

Abstract: A memory system includes a memory device including memory blocks and a memory controller coupled to the memory device. The memory controller is configured to in response to a failure for reading operation on a memory block of the memory blocks, determine read bias groups based on a number of erase cycles of the memory block and a storage status of the memory block, and send one or more read retry commands to the memory device. The one or more read retry commands indicate the memory device to perform one or more read operations on the memory block based on the read bias groups.

Abstract: Wire grid polarizer and manufacturing method thereof are provided, the wire grid polarizer includes: substrate; first wire grid formed on substrate, including first wire grid reflection strips arranged parallel to each other and at equal intervals; second wire grid formed at a side of first wire grid away from substrate, including second wire grid reflection strips arranged in parallel to each other and at equal intervals; second wire grid reflection strips are in one-to-one correspondence with first wire grid reflection strips; orthographic projections of second wire grid reflection strip onto substrate falls within orthographic projections of corresponding first wire grid reflection strip onto substrate; wire width of second wire grid reflection strip is less than that of first wire grid reflection strip; and wire spacing of second wire grid reflection strip is greater than that of the first wire grid reflection strip.

Abstract: A semiconductor device package, along with methods of forming such, are described. The semiconductor device package includes a first semiconductor device structure having a first substrate, two first devices disposed on the first substrate, a first interconnection structure disposed over the first substrate and the two first devices, and a first thermal feature disposed through the first substrate and the first interconnection structure. The semiconductor device package further includes a second semiconductor device structure disposed over the first semiconductor device structure having a second interconnection structure disposed over the first interconnection structure, a second substrate disposed over the second interconnection structure, two second devices disposed between the second substrate and the second interconnection structure, and a second thermal feature disposed through the second substrate and the second interconnection structure.

Abstract: A semiconductor device structure and methods of forming the same are described. The structure includes a first semiconductor material disposed over a substrate and a dielectric layer disposed on the first semiconductor material. The dielectric layer includes a dopant. The structure further includes a second semiconductor material disposed on the dielectric layer, a first semiconductor layer in contact with the second semiconductor material, and a first dielectric spacer in contact with the first semiconductor layer, wherein the first dielectric spacer includes the dopant.

Abstract: A minimum IC operating voltage searching method includes acquiring a corner type of an IC, acquiring ring oscillator data of the IC, generating a first prediction voltage according to the corner type and the ring oscillator data by using a training model, generating a second prediction voltage according to the ring oscillator data by using a non-linear regression approach under an N-ordered polynomial, and generating a predicted minimum IC operating voltage according to the first prediction voltage and the second prediction voltage. N is a positive integer.

Abstract: A memory device includes a memory block including memory strings, bit lines coupled to the memory strings, dummy word lines coupled to the dummy cells, first select lines coupled to the first select transistors, and a peripheral circuit coupled to the bit lines, the dummy word lines, and the first select lines. Each of the memory strings includes memory cells, first select transistors, and dummy cells. The peripheral circuit is configured to apply a turn on voltage on the first select lines, and apply a program voltage on a first dummy word line of the dummy word lines to program all dummy cells coupled to the first dummy word line.

Abstract: A semiconductor structure includes a circuit substrate, a semiconductor die, and a cover. The semiconductor die is disposed on the circuit substrate. The cover is disposed over the semiconductor die and over the circuit substrate. The cover comprises a lid portion and a support portion. The structure includes a first adhesive bonding the support portion to the circuit substrate and a second adhesive bonding the support portion and the lid portion.