Patents by Inventor Kang Huang
Kang Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20250149486Abstract: A method includes forming a first conductive pillar on an interposer; forming a second conductive pillar on the interposer, wherein the second conductive pillar includes a barrier layer; bonding a first semiconductor device to the first conductive pillar by a first bonding region that includes more inter-metallic compound than solder; and bonding the first semiconductor device to the second conductive pillar by a second bonding region that includes more solder than inter-metallic compound.Type: ApplicationFiled: February 6, 2024Publication date: May 8, 2025Inventors: Yao-Jen Chang, Chung-Yu Lu, Ping-Kang Huang, Sao-Ling Chiu, Hsien-Pin Hu
-
Publication number: 20250142328Abstract: This application provides methods and apparatuses, and relates to the field of communication technologies, A method includes a first network element receives a first message from an access network device, where the first message includes identification information of a terminal, identifies a terminal type, and if the terminal type is a first terminal type, sends the identification information of the terminal to an application server, or if the terminal type is a second terminal type, triggers an authentication procedure of the terminal.Type: ApplicationFiled: December 30, 2024Publication date: May 1, 2025Inventors: Kang Huang, Hualin Zhu, Yishan Xu, Hantao Li
-
Patent number: 12283541Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, a molding compound and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The at least one semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The molding compound is disposed over the interposer and laterally encapsulates the at least one semiconductor die. The molding compound laterally wraps around the interposer and the molding compound at least physically contacts a portion of the sidewalls of the interposer. The connectors are disposed on the second surface of the interposer, and are electrically connected with the at least one semiconductor die through the interposer.Type: GrantFiled: January 14, 2024Date of Patent: April 22, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Ming Huang, Ping-Kang Huang, Sao-Ling Chiu, Shang-Yun Hou
-
Publication number: 20250119961Abstract: A communication method and apparatus are provided. The method includes: A first communication apparatus receives a first request, where the first request indicates the first communication apparatus to obtain information about a first tag. The first communication apparatus obtains the information about the first tag based on the first request, where the information about the first tag includes an identifier of the first tag. According to the method, after obtaining the information about the first tag, the first communication apparatus determines the corresponding first communication session for the information about the first tag, so that it can be ensured that the first communication apparatus can effectively and accurately transmit the information about the first tag by using the first communication session.Type: ApplicationFiled: December 19, 2024Publication date: April 10, 2025Inventors: Kang HUANG, Hualin ZHU, Yishan XU, Hantao LI
-
Patent number: 12261133Abstract: A method is provided for forming an integrated circuit (IC) chip package structure. The method includes: providing an interposer having a front surface and a back surface, the interposer comprising a substrate, at least one routing region, and at least one non-routing region; forming at least one warpage-reducing trench in the at least one non-routing region, wherein the at least one warpage-reducing trench extends from the front surface of the interposer to a first depth, the first depth smaller than a thickness between the front surface and the back surface of the interposer; depositing a warpage-relief material in the at least one warpage-reducing trench; and bonding the group of IC dies to the front surface of the interposer.Type: GrantFiled: April 8, 2024Date of Patent: March 25, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Yang Hsieh, Chien-Chang Lee, Chia-Ping Lai, Wen-Chung Lu, Cheng-Kang Huang, Mei-Shih Kuo, Chih-Ai Huang
-
Publication number: 20250069980Abstract: A semiconductor structure includes a circuit substrate, a semiconductor die, and a cover. The semiconductor die is disposed on the circuit substrate. The cover is disposed over the semiconductor die and over the circuit substrate. The cover comprises a lid portion and a support portion. The structure includes a first adhesive bonding the support portion to the circuit substrate and a second adhesive bonding the support portion and the lid portion.Type: ApplicationFiled: November 14, 2024Publication date: February 27, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wensen Hung, Ping-Kang Huang, Sao-Ling Chiu, Tsung-Yu Chen, Tsung-Shu Lin, Chien-Yuan Huang, Chen-Hsiang Lao
-
Publication number: 20250024332Abstract: This application provides a communication method and apparatus, to provide a non-3GPP path switching solution in a multi-access session. The method includes: A session management device determines to perform non-3GPP transmission path switching in a multi-access session, where the multi-access session includes at least two non-3GPP transmission paths; and the session management device sends a first offloading rule to a user plane device, where the first offloading rule is for supporting the user plane device in determining a first target transmission path from at least two non-3GPP transmission paths. According to the method, when it is determined to perform non-3GPP path switching, UE and a UPF can select, in a switching process based on a new offloading rule, an appropriate path from a plurality of non-3GPP access paths for data transmission, to ensure service continuity during session switching.Type: ApplicationFiled: September 26, 2024Publication date: January 16, 2025Inventors: Kang HUANG, Yishan XU
-
Publication number: 20250024250Abstract: This application relates to the field of communication technologies, and provides an access network device determining method and an apparatus, to resolve may fail to access, when requesting to access a network through the non-3GPP access network device, a network slice that the terminal device requests to access. The method includes: The terminal device sends a first message to a mobility management device through a first access network device, where the first message includes an identifier of at least one network slice, and indicates a request for accessing the network slice; receives a second message through the first access network device or a second access network device, where the second message includes information about the second access network device, and indicates that the second access network device supports one or more of the at least one network slice; and establishes a connection to the second access network device.Type: ApplicationFiled: September 27, 2024Publication date: January 16, 2025Inventors: Yishan XU, Fangyuan ZHU, Kang HUANG
-
Publication number: 20250003163Abstract: A snow thrower includes a body including a working assembly; a handle for a user to hold and connected to the body; and an energy device for providing the snow thrower with electrical energy. The snow thrower further includes a control module having a power-on state for being powered by the energy device; an operating device configured to be operated by the user to send a temperature control signal to a wireless communication module when separated from the snow thrower; and the wireless communication module configured to transmit the temperature control signal to the control module. The control module is switched to the power-on state according to the temperature control signal, and the control module in the power-on state controls the temperature of at least part of the snow thrower.Type: ApplicationFiled: May 20, 2024Publication date: January 2, 2025Inventors: Xiaozhe Zhao, Kang Huang, Peng Wang, Juntao Zheng
-
Publication number: 20240429312Abstract: Provided are semiconductor devices and methods for fabricating such devices. An exemplary method includes forming fin structures separated by an isolation material; depositing a high-k material over the fin structures and isolation material, wherein the high-k material includes lower portions located between fin structures and an upper portion located above the fin structures; depositing a topography-improving capping layer over the high-k material; performing a chemical mechanical planarization (CMP) process to remove the capping layer and the upper portion of the high-k material and to define high-k insulation segments.Type: ApplicationFiled: June 20, 2023Publication date: December 26, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kang Huang, Deng-Ming Juo, Wan-Chun Pan, Shich-Chang Suen
-
Patent number: 12175644Abstract: The systems and methods described can include approaches to calibrate head-mounted displays for improved viewing experiences. Some methods include receiving data of a first target image associated with an undeformed state of a first eyepiece of a head-mounted display device; receiving data of a first captured image associated with deformed state of the first eyepiece of the head-mounted display device; determining a first transformation that maps the first captured image to the image; and applying the first transformation to a subsequent image for viewing on the first eyepiece of the head-mounted display device.Type: GrantFiled: August 24, 2023Date of Patent: December 24, 2024Assignee: Magic Leap, Inc.Inventors: Lionel Ernest Edwin, Samuel A. Miller, Etienne Gregoire Grossmann, Brian Christopher Clark, Michael Robert Johnson, Wenyi Zhao, Nukul Sanjay Shah, Po-Kang Huang
-
Publication number: 20240422713Abstract: A communication method and an apparatus to reduce signaling overheads in a registration process of a terminal device. The method includes: receiving a registration request from a read/write device, sending a transmission request to an application network element, and notifying the read/write device of a registration success. The registration request includes identification information of the terminal device, the registration request is used to request to register the identification information with a network, the transmission request includes the identification information, and the transmission request is used to request to transmit the identification information to the application network element.Type: ApplicationFiled: August 28, 2024Publication date: December 19, 2024Applicant: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Kang HUANG, Hualin ZHU, Yishan XU
-
Patent number: 12170237Abstract: A semiconductor structure includes a circuit substrate, a semiconductor die, and a cover. The semiconductor die is disposed on the circuit substrate. The cover is disposed over the semiconductor die and over the circuit substrate. The cover comprises a lid portion and a support portion. The structure includes a first adhesive bonding the support portion to the circuit substrate and a second adhesive bonding the support portion and the lid portion.Type: GrantFiled: June 14, 2023Date of Patent: December 17, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wensen Hung, Ping-Kang Huang, Sao-Ling Chiu, Tsung-Yu Chen, Tsung-Shu Lin, Chien-Yuan Huang, Chen-Hsiang Lao
-
Publication number: 20240395602Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The method includes receiving a semiconductor substrate having a first region and a second region; forming a dielectric layer over the semiconductor substrate; removing portions of the dielectric layer to form a dielectric structure in the first region, wherein the dielectric structure includes a base structure and a plurality of first isolation structures over the base structure; forming a semiconductor layer covering the first region and the second region; removing a portion of the semiconductor layer to expose a top surface of the plurality of first isolation structures; and forming a plurality of second isolation structures in the second region.Type: ApplicationFiled: July 29, 2024Publication date: November 28, 2024Inventors: Soon-Kang Huang, Hsing-Chi Chen
-
Publication number: 20240395639Abstract: A package comprises an interposer, comprising an interposer substrate including at least one layer, and a plurality of RDLs formed through at least a portion of the interposer substrate. The package also includes a die device structure comprising at least one device die, and a first test line (TL) structure interposed between the interposer and the die device structure. The first TL structure includes at least one first test line electrically coupled to the at least one device die, at least a portion of the at least one first test line extending beyond a peripheral edge of the die device structure to provide an electrical interface with the at least one device die.Type: ApplicationFiled: July 31, 2024Publication date: November 28, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Yang Hsieh, Chien-Chang Lee, Chia-Ping Lai, Wen-Chung Lu, Cheng-Kang Huang, Mei-Shih Kuo, Alice Huang
-
Publication number: 20240383093Abstract: Embodiments of the present disclosure relate a CMP tool and methods for planarization a substrate. Particularly, embodiments of the present disclosure provide a substrate transporter for use in a CMP tool. The transporter may be used transport and/or carry substrates among various polishers and cleaners in a CMP tool while preventing the substrates from drying out during transportation. By keeping surfaces of the substrates wet during substrate waiting time or idle time in the CMP tool, embodiments of the present disclosure prevent many types of defects, such as byproducts, agglomerated abrasives, pad debris, slurry residues, from accumulate on the substrate surface during CMP processing, thus improve yields and device performance.Type: ApplicationFiled: July 31, 2024Publication date: November 21, 2024Inventors: Te-Chien HOU, Chih Hung CHEN, Kang HUANG, Wen-Pin LIAO, Shich-Chang SUEN, Kei-Wei CHEN
-
Publication number: 20240388896Abstract: This application provides an access network device selection method and an apparatus. In the method, the terminal device may indicate, to a DNS through one or more of first indication information, second indication information, and at least one GIN, whether the terminal device needs to support external authentication. Therefore, when selecting the non-3GPP access network device for the terminal device, the DNS may consider one or more of the first indication information, the second indication information, and the at least one GIN, to select the proper non-3GPP access network device for the terminal device based on the indication of the terminal device. For example, when the terminal device supports external authentication or needs to support external authentication, the DNS may select, for the terminal device, a non-3GPP access network device capable of performing external authentication.Type: ApplicationFiled: July 26, 2024Publication date: November 21, 2024Inventors: Yishan Xu, Kang Huang, Chuan Ma
-
Publication number: 20240371782Abstract: Board substrates, three-dimensional integrated circuit structures and methods of forming the same are disclosed. A board substrate includes a core layer, a first build-up layer, a second build-up layer, a first group of bumps, a second first group of bumps and at least one first underfill blocking wall. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The first group of bumps is disposed over the first build-up layer. The second first group of bumps is disposed over the first build-up layer. The at least one first underfill blocking wall is disposed over the first build-up layer and between the first group of bumps and the second group of bumps.Type: ApplicationFiled: July 17, 2024Publication date: November 7, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Yu Lu, Ping-Kang Huang, Sao-Ling Chiu
-
Publication number: 20240358280Abstract: An insertion needle structure includes a needle sharp and a needle body. The needle body is integrally connected to the needle sharp and has a receiving space for receiving the biosensor. The needle body includes a base wall, two side walls, two slope sections and two curved connecting sections. The side walls are located at two sides of the base wall, respectively, the side walls are at least partially nonparallel, and each of the side walls is at least partially flat. Each of the slope sections is connected between each of the side walls and the needle sharp, and each of the slope sections is curved. Each of the curved connecting sections is connected between each of the side walls and the base wall and between each of the slope sections and the base wall. The needle sharp extends from the base wall and the curved connecting sections.Type: ApplicationFiled: July 8, 2024Publication date: October 31, 2024Inventors: Li-Kang HUANG, Chieh-Hsing CHEN, Tsung-Da LI
-
Publication number: 20240363441Abstract: A method of manufacturing a semiconductor device having metal gates and the semiconductor device are disclosed. The method comprises providing a first sacrificial gate associated with a first conductive type transistor and a second sacrificial gate associated with a second conductive type transistor disposed over the substrate, wherein the first conductive type and the second conductive type are complementary; replacing the first sacrificial gate with a first metal gate structure; forming a patterned dielectric layer and/or a patterned photoresist layer to cover the first metal gate structure; and replacing the second sacrificial gate with a second metal gate structure. The method can improve gate height uniformity during twice metal gate chemical mechanical polish processes.Type: ApplicationFiled: July 11, 2024Publication date: October 31, 2024Inventors: TUNG-HUANG CHEN, YEN-YU CHEN, PO-AN CHEN, SOON-KANG HUANG