Patents by Inventor Kang-Hun Moon
Kang-Hun Moon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240063262Abstract: A semiconductor device is provided. The semiconductor device includes: an active pattern extending in on a substrate; nanosheets stacked on the active pattern; a gate electrode on the active pattern and surrounding the nanosheets; a source/drain trench on the active pattern adjacent the gate electrode; and a source/drain region in the source/drain trench, The source/drain region includes: a first layer provided along a sidewall and a bottom surface of the source/drain trench, the first layer having a first n-type impurity doped therein; a second layer on the first layer in the source/drain trench, the second layer having germanium (Ge) doped therein; and a third layer filling a remaining portion of the source/drain trench on the second layer, the third layer having a second n-type impurity doped therein.Type: ApplicationFiled: March 28, 2023Publication date: February 22, 2024Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong Uk Jeon, Kyung Ho Kim, Ki Hwan Kim, Kang Hun Moon, Cho Eun Lee
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Publication number: 20230402535Abstract: A semiconductor device includes; a substrate including an active pattern, a channel pattern on the active pattern, the channel pattern including a plurality of spaced apart and vertically stacked semiconductor patterns, a source/drain pattern connected to the plurality of semiconductor patterns, a gate electrode on the plurality of semiconductor patterns, the gate electrode including a portion interposed between adjacent ones of the plurality of semiconductor patterns, and an inner spacer interposed between the portion of the gate electrode and the source/drain pattern, wherein the inner spacer is crystalline metal oxide is expressed by a formula (MO), wherein (O) is an oxygen atom, and (M) is a metal atom selected from a group consisting of Mg, Be, and Ga.Type: ApplicationFiled: December 15, 2022Publication date: December 14, 2023Inventors: KYUNGHO KIM, KI HWAN KIM, KANG HUN MOON, CHOEUN LEE, YONGUK JEON
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Publication number: 20230387205Abstract: A semiconductor device includes a substrate including an active pattern; a source/drain pattern on the active pattern; a gate electrode on the active pattern; and a gate spacer on the source/drain pattern. The source/drain pattern includes a first semiconductor layer on the active pattern and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer includes a first inner sidewall and second inner sidewall on the second semiconductor layer. A distance between the first and second inner sidewalls of the first semiconductor layer decreases according as positions of two portions of the first semiconductor layer where the distance is measured become closer to the gate spacer decreases.Type: ApplicationFiled: January 23, 2023Publication date: November 30, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ki Hwan KIM, KYUNGHO KIM, KANG HUN MOON, CHOEUN LEE, Yonguk JEON
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Publication number: 20230387206Abstract: A semiconductor device comprises an active pattern including a lower pattern and a plurality of sheet patterns that are spaced apart from the lower pattern in a first direction, a plurality of gate structures disposed on the lower pattern to be spaced apart from each other in a second direction, each of the gate structures including a gate electrode and gate insulating films, source/drain recesses defined between adjacent gate structures and a source/drain pattern filling the source/drain recesses. Each source/drain pattern may include a first semiconductor liner, which extend along sidewalls and a bottom surface of the source/drain recesses, second semiconductor liners, which are on the first semiconductor liners and extend along the sidewalls and the bottom surface of the source/drain recesses, and a filling semiconductor film, which is on the second semiconductor liners and fills the source/drain recess.Type: ApplicationFiled: March 3, 2023Publication date: November 30, 2023Inventors: Ki Hwan KIM, Kyung Ho KIM, Kang Hun MOON, Cho Eun LEE, Yong Uk JEON
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Patent number: 11569350Abstract: Disclosed is a semiconductor device including a first active pattern that extends in a first direction on an active region of a substrate, a first source/drain pattern in a recess on an upper portion of the first active pattern, a gate electrode that runs across a first channel pattern on the upper portion of the first active pattern and extends in a second direction intersecting the first direction, and an active contact electrically connected to the first source/drain pattern.Type: GrantFiled: July 9, 2021Date of Patent: January 31, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sanggil Lee, Namkyu Cho, Seokhoon Kim, Kang Hun Moon, Hyun-Kwan Yu, Sihyung Lee
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Publication number: 20220415905Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.Type: ApplicationFiled: September 2, 2022Publication date: December 29, 2022Inventors: Jin-Bum KIM, Myung-Gil KANG, Kang-Hun MOON, Cho-Eun LEE, Su-Jin JUNG, Min-Hee CHOI, Yang XU, Dong-Suk SHIN, Kwan-Heum LEE, Hoi-Sung CHUNG
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Patent number: 11469237Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.Type: GrantFiled: April 18, 2019Date of Patent: October 11, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Bum Kim, Myung-Gil Kang, Kang-Hun Moon, Cho-Eun Lee, Su-Jin Jung, Min-Hee Choi, Yang Xu, Dong-Suk Shin, Kwan-Heum Lee, Hoi-Sung Chung
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Publication number: 20210336007Abstract: Disclosed is a semiconductor device including a first active pattern that extends in a first direction on an active region of a substrate, a first source/drain pattern in a recess on an upper portion of the first active pattern, a gate electrode that runs across a first channel pattern on the upper portion of the first active pattern and extends in a second direction intersecting the first direction, and an active contact electrically connected to the first source/drain pattern.Type: ApplicationFiled: July 9, 2021Publication date: October 28, 2021Inventors: SANGGIL LEE, NAMKYU CHO, SEOKHOON KIM, KANG HUN MOON, HYUN-KWAN YU, SIHYUNG LEE
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Patent number: 11069776Abstract: Disclosed is a semiconductor device including a first active pattern that extends in a first direction on an active region of a substrate, a first source/drain pattern in a recess on an upper portion of the first active pattern, a gate electrode that runs across a first channel pattern on the upper portion of the first active pattern and extends in a second direction intersecting the first direction, and an active contact electrically connected to the first source/drain pattern.Type: GrantFiled: February 13, 2020Date of Patent: July 20, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sanggil Lee, Namkyu Cho, Seokhoon Kim, Kang Hun Moon, Hyun-Kwan Yu, Sihyung Lee
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Publication number: 20210043730Abstract: Disclosed is a semiconductor device including a first active pattern that extends in a first direction on an active region of a substrate, a first source/drain pattern in a recess on an upper portion of the first active pattern, a gate electrode that runs across a first channel pattern on the upper portion of the first active pattern and extends in a second direction intersecting the first direction, and an active contact electrically connected to the first source/drain pattern.Type: ApplicationFiled: February 13, 2020Publication date: February 11, 2021Inventors: SANGGIL LEE, NAMKYU CHO, SEOKHOON KIM, KANG HUN MOON, HYUN-KWAN YU, SIHYUNG LEE
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Patent number: 10700203Abstract: A semiconductor device includes a plurality of active fins on a substrate, a gate electrode intersecting the plurality of active fins, and a source/drain region on the plurality of active fins, extending on a first side and a second side of the gate electrode. The source/drain region includes lower epitaxial layers on ones of the plurality of active fins. The lower epitaxial layers include germanium (Ge) having a first concentration. An upper epitaxial layer is on the lower epitaxial layers, and includes germanium (Ge) having a second concentration that is higher than the first concentration. The lower epitaxial layers have convex upper surfaces, and are connected to each other between the active fins.Type: GrantFiled: December 7, 2018Date of Patent: June 30, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Dong Woo Kim, Do Hee Kim, Hyo Jin Kim, Kang Hun Moon, Si Hyung Lee
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Publication number: 20190393347Abstract: A semiconductor device includes a plurality of active fins on a substrate, a gate electrode intersecting the plurality of active fins, and a source/drain region on the plurality of active fins, extending on a first side and a second side of the gate electrode. The source/drain region includes lower epitaxial layers on ones of the plurality of active fins. The lower epitaxial layers include germanium (Ge) having a first concentration. An upper epitaxial layer is on the lower epitaxial layers, and includes germanium (Ge) having a second concentration that is higher than the first concentration. The lower epitaxial layers have convex upper surfaces, and are connected to each other between the active fins.Type: ApplicationFiled: December 7, 2018Publication date: December 26, 2019Inventors: DONG WOO KIM, Do Hee Kim, Hyo Jin Kim, Kang Hun Moon, Si Hyung Lee
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Publication number: 20190244963Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.Type: ApplicationFiled: April 18, 2019Publication date: August 8, 2019Inventors: Jin-Bum Kim, Myung-Gil Kang, Kang-Hun Moon, Cho-Eun Lee, Su-Jin Jung, Min-Hee Choi, Yang Xu, Dong-Suk Shin, Kwan-Heum Lee, Hoi-Sung Chung
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Patent number: 10319859Abstract: A semiconductor device is disclosed. The device includes a substrate including an active region defined by a device isolation layer, a fin pattern protruding from the substrate and extending in a first direction, the fin pattern including a gate fin region and a source/drain fin region, a gate pattern disposed on the gate fin region to extend in a second direction crossing the first direction, and a source/drain portion provided on a sidewall of the source/drain fin region. When measured in the second direction, a width of the source/drain fin region is different from a width in the second direction of the gate fin region.Type: GrantFiled: December 18, 2017Date of Patent: June 11, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sujin Jung, JinBum Kim, Kang Hun Moon, Kwan Heum Lee, Byeongchan Lee, Choeun Lee, Yang Xu
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Patent number: 10297601Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.Type: GrantFiled: November 15, 2016Date of Patent: May 21, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Bum Kim, Myung-Gil Kang, Kang-Hun Moon, Cho-Eun Lee, Su-Jin Jung, Min-Hee Choi, Yang Xu, Dong-Suk Shin, Kwan-Heum Lee, Hoi-Sung Chung
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Patent number: 10128112Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a dummy gate electrode on a substrate, forming a trench on a side surface of the dummy gate electrode, performing a bake process of removing an impurity from the trench and forming a source/drain in the trench, wherein the bake process comprises a first stage and a second stage following the first stage, an air pressure in which the substrate is disposed during the first stage is different from an air pressure in which the substrate is disposed during the second stage, and the bake process is performed while the substrate is on a stage rotating the substrate, wherein a revolution per minute (RPM) of the substrate during the first stage is different from a revolution per minute (RPM) of the substrate during the second stage.Type: GrantFiled: May 16, 2017Date of Patent: November 13, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Cho Eun Lee, Jin Bum Kim, Kang Hun Moon, Jae Myung Choe, Sun Jung Kim, Dong Suk Shin, Il Gyou Shin, Jeong Ho Yoo
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Patent number: 10068993Abstract: Methods of forming an integrated circuit device are provided. The methods may include forming a gate structure on a substrate, forming a first etch mask on a sidewall of the gate structure, anisotropically etching the substrate using the gate structure and the first etch mask as an etch mask to form a preliminary recess in the substrate, forming a sacrificial layer in the preliminary recess, forming a second etch mask on the first etch mask, etching the sacrificial layer and the substrate beneath the sacrificial layer using the gate structure and the first and second etch masks as an etch mask to form a source/drain recess in the substrate, and forming a source/drain in the source/drain recess. A sidewall of the source/drain recess may be recessed toward the gate structure relative to an outer surface of the second etch mask.Type: GrantFiled: January 15, 2018Date of Patent: September 4, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: JinBum Kim, Kang Hun Moon, Choeun Lee, Sujin Jung, Yang Xu
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Publication number: 20180151705Abstract: Methods of forming an integrated circuit device are provided. The methods may include forming a gate structure on a substrate, forming a first etch mask on a sidewall of the gate structure, anisotropically etching the substrate using the gate structure and the first etch mask as an etch mask to form a preliminary recess in the substrate, forming a sacrificial layer in the preliminary recess, forming a second etch mask on the first etch mask, etching the sacrificial layer and the substrate beneath the sacrificial layer using the gate structure and the first and second etch masks as an etch mask to form a source/drain recess in the substrate, and forming a source/drain in the source/drain recess. A sidewall of the source/drain recess may be recessed toward the gate structure relative to an outer surface of the second etch mask.Type: ApplicationFiled: January 15, 2018Publication date: May 31, 2018Inventors: JinBum KIM, Kang Hun MOON, Choeun LEE, Sujin JUNG, Yang XU
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Publication number: 20180108779Abstract: A semiconductor device is disclosed. The device includes a substrate including an active region defined by a device isolation layer, a fin pattern protruding from the substrate and extending in a first direction, the fin pattern including a gate fin region and a source/drain fin region, a gate pattern disposed on the gate fin region to extend in a second direction crossing the first direction, and a source/drain portion provided on a sidewall of the source/drain fin region. When measured in the second direction, a width of the source/drain fin region is different from a width in the second direction of the gate fin region.Type: ApplicationFiled: December 18, 2017Publication date: April 19, 2018Inventors: Sujin JUNG, JinBum KIM, KANG HUN MOON, KWAN HEUM LEE, BYEONGCHAN LEE, Choeun LEE, Yang XU
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Publication number: 20180096845Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a dummy gate electrode on a substrate, forming a trench on a side surface of the dummy gate electrode, performing a bake process of removing an impurity from the trench and forming a source/drain in the trench, wherein the bake process comprises a first stage and a second stage following the first stage, an air pressure in which the substrate is disposed during the first stage is different from an air pressure in which the substrate is disposed during the second stage, and the bake process is performed while the substrate is on a stage rotating the substrate, wherein a revolution per minute (RPM) of the substrate during the first stage is different from a revolution per minute (RPM) of the substrate during the second stage.Type: ApplicationFiled: May 16, 2017Publication date: April 5, 2018Inventors: Cho Eun LEE, Jin Bum KIM, Kang Hun MOON, Jae Myung CHOE, Sun Jung KIM, Dong Suk SHIN, IL GYOU SHIN, Jeong Ho YOO