Patents by Inventor Kang-Hyun Baek
Kang-Hyun Baek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230281375Abstract: A semiconductor design automation system comprises a simulator configured to generate simulation data, a recovery module configured to correct a sampling error of the simulation data to generate recovery simulation data, a hardware data module configured to generate real data, a preprocessing module configured to preprocess the real data to generate preprocessed real data, a database configured to store the recovery simulation data and the preprocessed real data, a first graphic user interface including an automatic simulation generator configured to generate a machine learning model of the recovery simulation data and the preprocessed real data and generate predicted real data therefrom, and a second graphic user interface including a visualization unit configured to generate a visualized virtualization process result from the machine learning model.Type: ApplicationFiled: May 12, 2023Publication date: September 7, 2023Inventors: Song-Yi Han, Jae Min Kim, Jae Ho Kim, Ji-Seong Doh, Kang-Hyun Baek, Young Kyou Shin, Seong Hun Jang, Young Jun Cho, Yun Ji Choi
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Patent number: 11687696Abstract: A semiconductor design automation system comprises a simulator configured to generate simulation data, a recovery module configured to correct a sampling error of the simulation data to generate recovery simulation data, a hardware data module configured to generate real data, a preprocessing module configured to preprocess the real data to generate preprocessed real data, a database configured to store the recovery simulation data and the preprocessed real data, a first graphic user interface including an automatic simulation generator configured to generate a machine learning model of the recovery simulation data and the preprocessed real data and generate predicted real data therefrom, and a second graphic user interface including a visualization unit configured to generate a visualized virtualization process result from the machine learning model.Type: GrantFiled: August 6, 2021Date of Patent: June 27, 2023Inventors: Song-Yi Han, Jae Min Kim, Jae Ho Kim, Ji-Seong Doh, Kang-Hyun Baek, Young Kyou Shin, Seong Hun Jang, Young Jun Cho, Yun Ji Choi
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Publication number: 20220138397Abstract: A semiconductor design automation system comprises a simulator configured to generate simulation data, a recovery module configured to correct a sampling error of the simulation data to generate recovery simulation data, a hardware data module configured to generate real data, a preprocessing module configured to preprocess the real data to generate preprocessed real data, a database configured to store the recovery simulation data and the preprocessed real data, a first graphic user interface including an automatic simulation generator configured to generate a machine learning model of the recovery simulation data and the preprocessed real data and generate predicted real data therefrom, and a second graphic user interface including a visualization unit configured to generate a visualized virtualization process result from the machine learning model.Type: ApplicationFiled: August 6, 2021Publication date: May 5, 2022Inventors: Song-Yi Han, Jae Min Kim, Jae Ho Kim, Ji-Seong Doh, Kang-Hyun Baek, Young Kyou Shin, Seong Hun Jang, Young Jun Cho, Yun Ji Choi
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Patent number: 10700193Abstract: A power device includes a drift layer of a second conductivity type located on a semiconductor layer of a first conductivity type, a first source region of the second conductivity type and a second source region of the second conductivity type, located on the drift layer to be apart from each other, and a gate electrode on the drift layer between the first and second source regions with a gate insulating layer between the gate electrode and the drift layer, wherein the gate electrode includes a first gate electrode and a second gate electrode adjacent to the first source region and the second source region, respectively, and a third gate electrode between the first and second gate electrodes, wherein the third gate electrode is floated or grounded.Type: GrantFiled: May 16, 2019Date of Patent: June 30, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-hyun Yoo, Ui-hui Kwon, Da-won Jeong, Jae-ho Kim, Jun-hyeok Kim, Kang-hyun Baek, Kyu-ok Lee
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Publication number: 20200144411Abstract: A power device includes a drift layer of a second conductivity type located on a semiconductor layer of a first conductivity type, a first source region of the second conductivity type and a second source region of the second conductivity type, located on the drift layer to be apart from each other, and a gate electrode on the drift layer between the first and second source regions with a gate insulating layer between the gate electrode and the drift layer, wherein the gate electrode includes a first gate electrode and a second gate electrode adjacent to the first source region and the second source region, respectively, and a third gate electrode between the first and second gate electrodes, wherein the third gate electrode is floated or grounded.Type: ApplicationFiled: May 16, 2019Publication date: May 7, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Jae-hyun YOO, Ui-hui Kwon, Da-won Jeong, Jae-ho Kim, Jun-hyeok Kim, Kang-hyun Baek, Kyu-ok Lee
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Patent number: 9627376Abstract: A semiconductor device includes first and second memory cell regions adjacent to each other on a substrate. At least one active base and a shallow trench isolation may be sequentially laminated at a boundary between the first and second memory cell regions. First and second active fins are formed on respective sides of the shallow trench isolation, and the first and second active fins projecting from the active base. At least one deep trench isolation is formed on one side of the active base.Type: GrantFiled: May 19, 2014Date of Patent: April 18, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Tae-Joong Song, Jae-Ho Park, Kang-Hyun Baek
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Patent number: 9576953Abstract: A layout design system for designing a semiconductor device includes a processor, a storage module storing an intermediate design, and a correction module used by the processor to correct the intermediate design. The intermediate design includes an active region and dummy designs on the active region. Each dummy design includes a dummy structure and dummy spacers disposed at opposite sides of the dummy structure. The correction module is configured to alter widths of regions of at least some of the dummy designs. The corrected design is used to produce a semiconductor device having an active fin, a hard mask layer disposed on the active fin, a gate structure crossing the over the hard mask layer, and a spacer disposed on at least one side of the gate structure. The hard mask layer, and the active fin, are provided with widths that vary due to the dummy designs.Type: GrantFiled: September 17, 2014Date of Patent: February 21, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Kang-Hyun Baek, Jin-Hyun Noh, Tae-Joong Song, Gi-Young Yang, Sang-Kyu Oh
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Patent number: 9478536Abstract: A semiconductor device with fin capacitors is disclosed. The device includes a substrate including a first region and a second region; first and second active fins at the first and second regions, respectively, of the substrate; a device isolation layer in a first trench between the first active fins; first and second gate electrodes that cross the first and second active fins, respectively; a first dielectric layer between the first active fins and the first gate electrode to extend along the first gate electrode, and a second dielectric layer between the second active fins and the second gate electrode to extend along the second gate electrode. The first dielectric layer is spaced apart from a bottom surface of the first trench by the device isolation layer between the bottom surface of the first trench and the first dielectric layer. The second dielectric layer is in direct contact with a bottom surface of a second trench between the second active fins.Type: GrantFiled: December 8, 2015Date of Patent: October 25, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Kang-hyun Baek, Sang-kyu Oh, Yongwoo Jeon
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Publication number: 20160163694Abstract: A semiconductor device with fin capacitors is disclosed. The device includes a substrate including a first region and a second region; first and second active fins at the first and second regions, respectively, of the substrate; a device isolation layer in a first trench between the first active fins; first and second gate electrodes that cross the first and second active fins, respectively; a first dielectric layer between the first active fins and the first gate electrode to extend along the first gate electrode, and a second dielectric layer between the second active fins and the second gate electrode to extend along the second gate electrode. The first dielectric layer is spaced apart from a bottom surface of the first trench by the device isolation layer between the bottom surface of the first trench and the first dielectric layer. The second dielectric layer is in direct contact with a bottom surface of a second trench between the second active fins.Type: ApplicationFiled: December 8, 2015Publication date: June 9, 2016Inventors: Kang-hyun Baek, Sang-kyu Oh, Yongwoo Jeon
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Publication number: 20160141388Abstract: In a method, a dummy gate layer structure and a mask layer are formed on a substrate. The mask layer is patterned to form masks. Spacers are formed on sidewalls of the mask. A dummy gate mask is formed between the spacers. The dummy gate layer structure is patterned using the dummy gate mask to form dummy gate structures. The dummy gate structure is replaced with a gate structure. When the mask is formed, an initial layout of masks extending in a first direction is designed. An offset bias in a second direction is provided for a specific region of the initial layout to design a final layout having a width in the second direction varying along the first direction. The mask layer is patterned according to the final layout to form the masks having a width varying along the first direction.Type: ApplicationFiled: September 17, 2015Publication date: May 19, 2016Inventors: Kang-Hyun BAEK, Kwan-Jae SONG, Jong-Sung JEON
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Patent number: 9324832Abstract: In a method, a dummy gate layer structure and a mask layer are formed on a substrate. The mask layer is patterned to form masks. Spacers are formed on sidewalls of the mask. A dummy gate mask is formed between the spacers. The dummy gate layer structure is patterned using the dummy gate mask to form dummy gate structures. The dummy gate structure is replaced with a gate structure. When the mask is formed, an initial layout of masks extending in a first direction is designed. An offset bias in a second direction is provided for a specific region of the initial layout to design a final layout having a width in the second direction varying along the first direction. The mask layer is patterned according to the final layout to form the masks having a width varying along the first direction.Type: GrantFiled: September 17, 2015Date of Patent: April 26, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Kang-Hyun Baek, Kwan-Jae Song, Jong-Sung Jeon
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Patent number: 9306070Abstract: A semiconductor device includes: active fins protruding from an active layer and extending in a first direction; a gate structure on the active fins extending in a second direction intersecting the first direction; and a spacer on at least one side of the gate structure, wherein each of the active fins includes a first region and a second region adjacent to the first direction in the first direction, and a width of the first region in the second direction is different from a width of the second region in the second direction.Type: GrantFiled: August 22, 2014Date of Patent: April 5, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Kang-Hyun Baek, Sung-Hyun Park, Sang-Hoon Baek, Tae-Joong Song
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Publication number: 20150221644Abstract: A layout design system for designing a semiconductor device includes a processor, a storage module storing an intermediate design, and a correction module used by the processor to correct the intermediate design. The intermediate design includes an active region and dummy designs on the active region. Each dummy design includes a dummy structure and dummy spacers disposed at opposite sides of the dummy structure. The correction module is configured to alter widths of regions of at least some of the dummy designs. The corrected design is used to produce a semiconductor device having an active fin, a hard mask layer disposed on the active fin, a gate structure crossing the over the hard mask layer, and a spacer disposed on at least one side of the gate structure. The hard mask layer, and the active fin, are provided with widths that vary due to the dummy designs.Type: ApplicationFiled: September 17, 2014Publication date: August 6, 2015Inventors: KANG-HYUN BAEK, JIN-HYUN NOH, TAE-JOONG SONG, GI-YOUNG YANG, SANG-KYU OH
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Publication number: 20150137262Abstract: A semiconductor device includes: active fins protruding from an active layer and extending in a first direction; a gate structure on the active fins extending in a second direction intersecting the first direction; and a spacer on at least one side of the gate structure, wherein each of the active fins includes a first region and a second region adjacent to the first direction in the first direction, and a width of the first region in the second direction is different from a width of the second region in the second direction.Type: ApplicationFiled: August 22, 2014Publication date: May 21, 2015Inventors: Kang-Hyun Baek, Sung-Hyun Park, Sang-Hoon Baek, Tae-Joong Song
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Publication number: 20140374828Abstract: A semiconductor device includes first and second memory cell regions adjacent to each other on a substrate. At least one active base and a shallow trench isolation may be sequentially laminated at a boundary between the first and second memory cell regions. First and second active fins are formed on respective sides of the shallow trench isolation, and the first and second active fins projecting from the active base. At least one deep trench isolation is formed on one side of the active base.Type: ApplicationFiled: May 19, 2014Publication date: December 25, 2014Inventors: Tae-Joong SONG, Jae-Ho PARK, Kang-Hyun BAEK
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Patent number: 8785992Abstract: An example embodiment relates to a light-guiding structure. The light-guiding structure may include a bottom surface and a sidewall defined by a first, a second, and a third insulating layer disposed on a semiconductor substrate. The bottom surface may be parallel to a main surface of the semiconductor substrate and may be disposed in the first insulating layer. The sidewall may penetrate the second and third insulating layers to extend to the first insulating layer, and the sidewall may be tapered with respect to the main surface of semiconductor substrate. The light-guiding structure may be included in a image sensor. The image sensor may be included in a processor-based system.Type: GrantFiled: July 20, 2011Date of Patent: July 22, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Kang-Hyun Baek, Sang-Il Jung, Jin-Ho Kim, Jeong-Ho Lee, Jeong-Bin Kim
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Publication number: 20120018833Abstract: An example embodiment relates to a light-guiding structure. The light-guiding structure may include a bottom surface and a sidewall defined by a first, a second, and a third insulating layer disposed on a semiconductor substrate. The bottom surface may be parallel to a main surface of the semiconductor substrate and may be disposed in the first insulating layer. The sidewall may penetrate the second and third insulating layers to extend to the first insulating layer, and the sidewall may be tapered with respect to the main surface of semiconductor substrate. The light-guiding structure may be included in a image sensor. The image sensor may be included in a processor-based system.Type: ApplicationFiled: July 20, 2011Publication date: January 26, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kang-Hyun Baek, Sang-Il Jung, Jin-Ho Kim, Jeong-Ho Lee, Jeong-Bin Kim
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Patent number: 7106938Abstract: A method of making a photonic crystal includes obtaining single spheres for use in making a self assembled opal structure. Spherical particles are placed centrifuge and separated from doublets using a relative difference in sedimentation velocity in response to centrifugal force. A method includes drawing a substrate through a meniscus at a declination to uniformly deposit spheres on the substrate. Three-dimensional photonic crystals including buried waveguides are also provided.Type: GrantFiled: March 16, 2004Date of Patent: September 12, 2006Assignees: Regents of the University of Minnesota, 3M Innovative Properties CompanyInventors: Kang-Hyun Baek, Anand Gopinath, H. Aaron Christmann
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Publication number: 20050206020Abstract: A method of making a photonic crystal includes obtaining single spheres for use in making a self assembled opal structure. Spherical particles are placed centrifuge and separated from doublets using a relative difference in sedimentation velocity in response to centrifugal force. A method includes drawing a substrate through a meniscus at a declination to uniformly deposit spheres on the substrate. Three-dimensional photonic crystals including buried waveguides are also provided.Type: ApplicationFiled: March 16, 2004Publication date: September 22, 2005Inventors: Kang-Hyun Baek, Anand Gopinath, H. Christmann
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Patent number: 5091480Abstract: Oligomers of polyarylene polyethethers (PAPE) having a mol wt Mn in the range from 1000 to about 10,000 are converted to monofunctionalized macromers, so as, in the first instance, to provide a reactive double bond (for example, a vinylbenzyl group) at only one end of the PAPE; and, in the second instance, to provide a triple bond (benzylethynyl group) at only one end of the PAPE. The macromer may be a polysulfone, a polyketone, or a copolymer containing both sulfone and ketone-containing units; or, the macromer may be monofunctionalized PPO. The synthesis of macromers with terminal double bonds is carried out with a fast and quantitative modified Williamson etherification of the PAPE with an electrophilic haloalkyl reactant ("HAR") such as chloromethylstyrene ("C1MS") in the presence of a major molar amount (more than 50 mol % based on the number of moles of OH group originally present in the oligomer) of a phase transfer catalyst such as tetrabutylammonium hydrogen sulfate ("TBAH").Type: GrantFiled: May 12, 1989Date of Patent: February 25, 1992Assignee: The B. F. Goodrich CompanyInventor: Virgil Percec