Abstract: A positive electrode active material for a lithium secondary battery has secondary micro particles having an average particle size (D50) of 1 to 10 ?m formed by agglomeration of primary macro particles having an average particle size (D50) of 0.5 to 3 ?m and a lithium-M oxide coating layer on all or part of a surface, wherein M is at least one selected from the group consisting of boron, cobalt, manganese and magnesium. The secondary macro particles have an average particle size (D50) of 5 to 20 ?m formed by agglomeration of primary micro particles having a smaller average particle size (D50) than the primary macro particles. The primary macro particles and the primary micro particles are represented by LiaNi1?b?c?dCobMncQdO2+?, wherein 1.0?a?1.5, 0<b<0.2, 0<c<0.2, 0?d?0.1, 0<b+c+d?0.2, ?0.1???1.0, and Q is at least one type of metal selected from the group consisting of Al, Mg, V, Ti and Zr.

Abstract: A positive electrode active material for a lithium secondary battery has a mixture of microparticles having a predetermined average particle size (D50) and macroparticles having a larger average particle size (D50) than the microparticles. The microparticles have the average particle size (D50) of 1 to 10 ?m and are at least one selected from the group consisting of particles having a carbon material coating layer on all or part of a surface of primary macroparticles having an average particle size (D50) of 1 ?m or more, particles having a carbon material coating layer on all or part of a surface of secondary particles formed by agglomeration of the primary macroparticles, and a mixture thereof. The macroparticles are secondary particles having an average particle size (D50) of 5 to 20 ?m formed by agglomeration of primary microparticles having a smaller average particle size (D50) than the primary macroparticles.

Abstract: Provided is a method of fabricating a semiconductor package. The method include providing a lower package with an inner solder ball, providing a conductive material on the inner solder ball to form an outer solder ball enclosing the inner solder ball, providing an upper package with an upper solder ball, on the lower package, performing a first process at a first temperature to join the upper solder ball to the outer solder ball, and performing a second process at a second temperature to unite the upper, inner, and outer solder balls into a connection terminal.

Abstract: An electric apparatus may include a plurality of electric patterns arranged on a substrate. Each of the electric patterns may include a pad for connection with a solder ball, an electrical trace laterally extending from a portion of the pad to allow an electrical signal to be transmitted from or to the pad, a first dummy trace laterally extending from other portion of the pad, and a first connection line connecting the first dummy trace to the electrical trace. The first dummy trace may be provided at a position deviated from a straight line connecting the pad to the electrical trace.

Abstract: Semiconductor packages include a first substrate including a central portion and a peripheral portion, at least one first central connection member attached to the central portion of the first substrate, and at least one first peripheral connection member attached to the peripheral portion of the first substrate. The first central connection member includes a first supporter and a first fusion conductive layer surrounding the first supporter.

Abstract: Provided is a method of fabricating a semiconductor package. The method include providing a lower package with an inner solder ball, providing a conductive material on the inner solder ball to form an outer solder ball enclosing the inner solder ball, providing an upper package with an upper solder ball, on the lower package, performing a first process at a first temperature to join the upper solder ball to the outer solder ball, and performing a second process at a second temperature to unite the upper, inner, and outer solder balls into a connection terminal.

Abstract: An electric apparatus may include a plurality of electric patterns arranged on a substrate. Each of the electric patterns may include a pad for connection with a solder ball, an electrical trace laterally extending from a portion of the pad to allow an electrical signal to be transmitted from or to the pad, a first dummy trace laterally extending from other portion of the pad, and a first connection line connecting the first dummy trace to the electrical trace. The first dummy trace may be provided at a position deviated from a straight line connecting the pad to the electrical trace.

Abstract: A semiconductor package including a lower package and an upper package provided may be provided. The lower package includes a lower package substrate, a lower semiconductor chip mounted thereon, and a lower mold layer provided on the lower package substrate. The upper package includes an upper package substrate and an upper semiconductor chip thereon. The lower mold layer includes a guide portion extending along a vertical direction from an edge of the lower package substrate toward the upper package.

Abstract: Semiconductor packages include a first substrate including a central portion and a peripheral portion, at least one first central connection member attached to the central portion of the first substrate, and at least one first peripheral connection member attached to the peripheral portion of the first substrate. The first central connection member includes a first supporter and a first fusion conductive layer surrounding the first supporter.

Abstract: A semiconductor package including a lower package and an upper package provided may be provided. The lower package includes a lower package substrate, a lower semiconductor chip mounted thereon, and a lower mold layer provided on the lower package substrate. The upper package includes an upper package substrate and an upper semiconductor chip thereon. The lower mold layer includes a guide portion extending along a vertical direction from an edge of the lower package substrate toward the upper package.

Abstract: Semiconductor packages include a first substrate including a central portion and a peripheral portion, at least one first central connection member attached to the central portion of the first substrate, and at least one first peripheral connection member attached to the peripheral portion of the first substrate. The first central connection member includes a first supporter and a first fusion conductive layer surrounding the first supporter.

Abstract: A dual-structure tube vessel and a method of producing the tube vessel are disclosed. The dual-structure tube vessel includes a cylindrical vessel body and a neck integrated with the vessel body into a single structure, and further includes: a body partitioning sheet provided in the vessel body and partitioning the interior of the vessel body into two sections; and a neck partitioning sheet provided in the neck and partitioning the interior of the neck into two sections. The vessel body and the body partitioning sheet may be fabricated using three sheets of material or one sheet of material. Further, the body partitioning sheet has a width equal to an inner circumference of a larger one of the two sections of the vessel body. Further, each of the vessel body and the body partitioning sheet is made of a threefold laminated sheet with a polyethylene/aluminum/polyethylene layered structure.