Abstract: Embodiments of the present disclosure provide a method, system, and computer program product for monitoring a service life of a chamber component. In one example, the method includes receiving one or more power measurements of a semiconductor processing chamber from one or more sensors positioned about the semiconductor processing chamber. The processor compares the one or more power measurements to one or more threshold values corresponding to the service life of the chamber component. The processor determines whether the one or more power measurements exceed the threshold values. If the processor determines that the one or more power measurements exceed the threshold values, the processor takes remedial measures for the service life of the chamber component.

Abstract: Embodiments of the present disclosure provide a method, system, and computer program product for monitoring a service life of a chamber component. In one example, the method includes receiving one or more power measurements of a semiconductor processing chamber from one or more sensors positioned about the semiconductor processing chamber. The processor compares the one or more power measurements to one or more threshold values corresponding to the service life of the chamber component. The processor determines whether the one or more power measurements exceed the threshold values. If the processor determines that the one or more power measurements exceed the threshold values, the processor takes remedial measures for the service life of the chamber component.

Abstract: Embodiments of the present disclosure provide a method, system, and computer program product for monitoring a service life of a chamber component. In one example, the method includes receiving one or more power measurements of a semiconductor processing chamber from one or more sensors positioned about the semiconductor processing chamber. The processor compares the one or more power measurements to one or more threshold values corresponding to the service life of the chamber component. The processor determines whether the one or more power measurements exceed the threshold values. If the processor determines that the one or more power measurements exceed the threshold values, the processor takes remedial measures for the service life of the chamber component.

Abstract: Embodiments of the present disclosure provide a method, system, and computer program product for monitoring a service life of a chamber component. In one example, the method includes receiving one or more power measurements of a semiconductor processing chamber from one or more sensors positioned about the semiconductor processing chamber. The processor compares the one or more power measurements to one or more threshold values corresponding to the service life of the chamber component. The processor determines whether the one or more power measurements exceed the threshold values. If the processor determines that the one or more power measurements exceed the threshold values, the processor takes remedial measures for the service life of the chamber component.

Abstract: Local and global reduction of critical dimension (CD) asymmetry in etch processing is described. In an example, a method of etching a wafer of to form a plurality of staircase structures with reduced local and global asymmetry involves forming a photoresist layer on a plurality of micron-scale semiconductor structures. The photoresist layer is then trimmed with a high pressure and pulsed plasma etch process performed in a reverse MESA mode.

Abstract: Local and global reduction of critical dimension (CD) asymmetry in etch processing is described. In an example, a method of etching a wafer of to form a plurality of staircase structures with reduced local and global asymmetry involves forming a photoresist layer on a plurality of micron-scale semiconductor structures. The photoresist layer is then trimmed with a high pressure and pulsed plasma etch process performed in a reverse MESA mode.

Abstract: Methods for forming an ultra thin structure using a method that includes multiple cycles of polymer deposition of photoresist (PDP) process and etching process. The embodiments described herein may be advantageously utilized to fabricate a submicron structure on a substrate having a critical dimension less than 55 nm and beyond. In one embodiment, a method of forming a submicron structure on a substrate may include providing a substrate having a patterned photoresist layer disposed on a film stack into an etch chamber, wherein the film stack includes at least a hardmask layer disposed on a dielectric layer, performing a polymer deposition process to deposit a polymer layer on the pattered photoresist layer, thus reducing a critical dimension of an opening in the patterned photoresist layer, and etching the underlying hardmask layer through the opening having the reduced dimension.

Abstract: Methods for cleaning a substrate are provided. In one embodiment, the method includes depositing a polymer on a substrate. A cleaning gas is provided to clean a frontside, a bevel edge, and a backside of the substrate. The cleaning gas may include various reactive chemicals such as H2 and N2 in one embodiment. In another embodiment, the cleaning gas may include H2 and H2O. Plasma is initiated from the cleaning gas and used to remove polymer that formed on a bevel edge, backside, or frontside of the substrate during semiconductor processing.

Abstract: Methods for forming an ultra thin structure using a method that includes multiple cycles of polymer deposition of photoresist (PDP) process and etching process. The embodiments described herein may be advantageously utilized to fabricate a submicron structure on a substrate having a critical dimension less than 55 nm and beyond. In one embodiment, a method of forming a submicron structure on a substrate may include providing a substrate having a patterned photoresist layer disposed on a film stack into an etch chamber, wherein the film stack includes at least a hardmask layer disposed on a dielectric layer, performing a polymer deposition process to deposit a polymer layer on the pattered photoresist layer, thus reducing a critical dimension of an opening in the patterned photoresist layer, and etching the underlying hardmask layer through the opening having the reduced dimension.

Abstract: A plasma reactor for processing a semiconductor workpiece, includes a reactor chamber having a chamber wall and containing a workpiece support for holding the semiconductor support, the electrode comprising a portion of the chamber wall, an RF power generator for supplying power at a frequency of the generator to the overhead electrode and capable of maintaining a plasma within the chamber at a desired plasma ion density level. The overhead electrode has a capacitance such that the overhead electrode and the plasma formed in the chamber at the desired plasma ion density resonate together at an electrode-plasma resonant frequency, the frequency of the generator being at least near the electrode-plasma resonant frequency. The reactor further includes a set of MERIE magnets surrounding the plasma process area overlying the wafer surface that produce a slowly circulating magnetic field which stirs the plasma to improve plasma ion density distribution uniformity.

Abstract: A plasma reactor for processing a semiconductor workpiece, includes reactor chamber having a chamber wall and containing a workpiece support for holding the semiconductor support, the electrode comprising a portion of the chamber wall, an RF power generator for supplying power at a frequency of the generator to the overhead electrode and capable of maintaining a plasma within the chamber at a desired plasma ion density level. The overhead electrode has a capacitance such that the overhead electrode and the plasma formed in the chamber at the desired plasma ion density resonate together at an electrode-plasma resonant frequency, the frequency of the generator being at least near the electrode-plasma resonant frequency. The reactor further includes a set of MERIE magnets surrounding the plasma process area overlying the wafer surface that produce a slowly circulating magnetic field which stirs the plasma to improve plasma ion density distribution uniformity.

Abstract: A method for removing residue from a layer of conductive material on a substrate is provided herein. In one embodiment, the method includes introducing a process gas into a vacuum chamber having a substrate surface with residue from exposure to a fluorine-containing environment. The process gas includes a hydrogen-containing gas. Optionally, the process gas may further include an oxygen-containing or a nitrogen containing gas. A plasma of the process gas is thereafter maintained in the vacuum chamber for a predetermined period of time to remove the residue from the surface. The temperature of the substrate is maintained at a temperature between about 10 degrees Celsius and about 90 degrees Celsius during the plasma step.

Abstract: A plasma reactor for processing a semiconductor workpiece, includes a reactor chamber having a chamber wall and containing a workpiece support for holding the semiconductor workpiece, an overhead electrode overlying said workpiece support, the electrode comprising a portion of said chamber wall, an RF power generator for supplying power at a frequency of said generator to said overhead electrode and capable of maintaining a plasma within said chamber at a desired plasma ion density level. The overhead electrode has a capacitance such that said overhead electrode and the plasma formed in said chamber at said desired plasma ion density resonate together at an electrode-plasma resonant frequency, said frequency of said generator being at least near said electrode-plasma resonant frequency.

Abstract: A plasma reactor for processing a semiconductor workpiece, includes a reactor chamber having a chamber wall and containing a workpiece support for holding the semiconductor support, the electrode comprising a portion of the chamber wall, an RF power generator for supplying power at a frequency of the generator to the overhead electrode and capable of maintaining a plasma within the chamber at a desired plasma ion density level. The overhead electrode has a capacitance such that the overhead electrode and the plasma formed in the chamber at the desired plasma ion density resonate together at an electrode-plasma resonant frequency, the frequency of the generator being at least near the electrode-plasma resonant frequency. The reactor further includes a set of MERIE magnets surrounding the plasma process area overlying the wafer surface that produce a slowly circulating magnetic field which stirs the plasma to improve plasma ion density distribution uniformity.

Abstract: A method of treating a dielectric layer having a low dielectric constant, where the dielectric layer has been processed in a manner that causes a change in the dielectric constant of an affected region of the layer. The treatment of the affected region may comprise etching, sputtering, annealing, or combinations thereof. The treatment returns the dielectric constant of the dielectric layer to substantially the dielectric constant that existed before processing.

Abstract: A plasma reactor for processing a semiconductor wafer includes a side wall and an overhead ceiling defining a chamber, a workpiece support cathode within the chamber having a working surface facing the ceiling for supporting a semiconductor workpiece, process gas inlets for introducing a process gas into the chamber and an RF bias power generator having a bias power frequency. There is a bias power feed point at the working surface and an RF conductor is connected between the RF bias power generator and the bias power feed point at the working surface. A dielectric sleeve surrounds a portion of the RF conductor, the sleeve having an axial length along the RF conductor, a dielectric constant and an axial location along the RF conductor, the length, dielectric constant and location of the sleeve being such that the sleeve provides a reactance that enhances plasma ion density uniformity over the working surface.

Abstract: A plasma reactor for processing a semiconductor workpiece, includes a reactor chamber having a chamber wall and containing a workpiece support for holding the semiconductor support, the electrode comprising a portion of the chamber wall, an RF power generator for supplying power at a frequency of the generator to the overhead electrode and capable of maintaining a plasma within the chamber at a desired plasma ion density level. The overhead electrode has a capacitance such that the overhead electrode and the plasma formed in the chamber at the desired plasma ion density resonate together at an electrode-plasma resonant frequency, the frequency of the generator being at least near the electrode-plasma resonant frequency. The reactor further includes a set of MERIE magnets surrounding the plasma process area overlying the wafer surface that produce a slowly circulating magnetic field which stirs the plasma to improve plasma ion density distribution uniformity.

Abstract: A plasma reactor for processing a semiconductor workpiece, includes a reactor chamber having a chamber wall and containing a workpiece support for holding the semiconductor support, the electrode comprising a portion of the chamber wall, an RF power generator for supplying power at a frequency of the generator to the overhead electrode and capable of maintaining a plasma within the chamber at a desired plasma ion density level. The overhead electrode has a capacitance such that the overhead electrode and the plasma formed in the chamber at the desired plasma ion density resonate together at an electrode-plasma resonant frequency, the frequency of the generator being at least near the electrode-plasma resonant frequency. The reactor further includes a set of MERIE magnets surrounding the plasma process area overlying the wafer surface that produce a slowly circulating magnetic field which stirs the plasma to improve plasma ion density distribution uniformity.

Abstract: A method of treating a dielectric layer having a low dielectric constant, where the dielectric layer has been processed in a manner that causes a change in the dielectric constant of an affected region of the layer. The treatment of the affected region may comprise etching, sputtering, annealing, or combinations thereof. The treatment returns the dielectric constant of the dielectric layer to substantially the dielectric constant that existed before processing.

Abstract: A method of etching a platinum electrode layer disposed on a substrate to produce a semiconductor device including a plurality of platinum electrodes. The method comprises heating the substrate to a temperature greater than about 150° C., and etching the platinum electrode layer by employing a plasma of an etchant gas comprising nitrogen and a halogen (e.g. chlorine), and a gas selected from the group consisting of a noble gas (e.g. argon), BCl3, HBr, SiCl4 and mixtures thereof. The substrate may be heated in a reactor chamber having a dielectric window including a deposit-receiving surface having a surface finish comprising a peak-to-valley roughness height with an average height value of greater than about 1000 Å.