Abstract: Described apparatuses and methods enable communication between a host device and a memory device to establish relative delays between different data lines. If data signals propagate along a bus with the same timing, simultaneous switching output (SSO) and crosstalk can adversely impact channel timing budget parameters. An example system includes an interconnect having multiple data lines that couple the host device to the memory device. In example operations, the host device can transmit to the memory device a command indicative of a phase offset between two or more data lines of the multiple data lines. The memory device can implement the command by transmitting or receiving signals via the interconnect with different relative phase offsets between data lines. The host device (e.g., a memory controller) can determine appropriate offsets for a given apparatus. Lengths of the offsets can vary. Further, a system can activate the phase offsets based on frequency.

Abstract: Described apparatuses and methods facilitate bus training with multiple dice, such as multiple memory dice. A controller can communicate with multiple dice to perform bus training by sending a test pattern and receiving in return a feedback pattern indicative of the bits detected by the dice. Because suitable signal timing can differ between dice, even those using the same bus, a controller may train each die separately from the others. In some situations, however, individualized training may be infeasible. To accommodate such situations, logic associated with two or more dice can combine, using at least one logical operation, bits as detected from the test pattern into a combined feedback pattern. A timing parameter that is jointly suitable for multiple dice can be determined, and the bus training may be concluded, responsive to the combined feedback pattern matching the test pattern. The multiple dice may be stacked or linked.

Abstract: An improved reactor for a high-temperature deposition reaction on seed particles is constructed with a fluidized bed which is divided into a heating zone and a reaction zone by a partition. Seed particles in the heating zone are fluidized by a carrier gas and are heated by microwaves. On the other hand, the reaction zone for the deposition reaction, through which reaction gases pass, is heated by particle mixing between the reaction zone and the upper section of the heating zone. Subsequently, a desired reaction temperature at the reaction zone is maintained stable without deteriorating the microwave heating of the heating zone.

Abstract: An improved method is provided for the deposition of high-purity silicon on silicon particles from silicon source gases in a fluidized bed reactor which is divided into a heating zone and a reaction zone by a partition. Silicon particles in the heating zone are fluidized by a carrier gas such as hydrogen and are heated by microwaves. On the other hand, the reaction zone for the deposition of silicon, through which reaction gases including the silicon source pass, is heated by particle mixing between the reaction zone and the upper section of the heating zone. Subsequently, a desired reaction temperature at the reaction zone is maintained stable without deteriorating the microwave heating of the heating zone.

Abstract: A jet pulverizing method is described for preparing silicon seed particles from silicon feed particles without contamination. The method comprises accelerating silicon feed particles by fluid jet energy and colliding them with each other within a pulverizing chamber to fracture or split them into small particles which are recovered for use as seed particles. The method is characterized by the technique that silicon particles fluidized within the pulverizing chamber are formed into a dilute-phase fluidized bed with low particle density. Thus, the generation of fine powders may be suppressed and additional sieving to separate larger particles is not required.

Abstract: A precise digitally-controlled variable attenuation circuit for adjusting e attenuation of a signal in an external circuit includes a signal magnitude detector, a resistance adjustment control, and a resistance divider network. The signal magnitude detector has lower and upper threshold limits representing a desired range of attenuation and is operable to receive and compare a control signal with the lower and upper threshold limits, and, in response thereto, produce either a first signal if the control signal is less than the lower threshold limit or a second signal if the control signal is greater than the upper threshold limit. The adjustment control is capable of receiving the first and second signals and is operable to produce either a digital count-down signal in response to the first signal or a digital count-up signal in response to the second signal. The resistance divider network has a fixed resistance and a digitally-adjustable device with a variable resistance.