Abstract: A micro-code engine with a linear shift register comprises at least one shift register and an execution unit. The shift registers contain a plurality of data cells, each of which store at least one data value. The shift register is operable to shift the data values from a first data cell to a second data cell as new data is input into the shift register. The execution unit is electrically coupled to the linear shift register such that when the execution unit performs an algorithm, the execution unit uses the data value stored in the second data cell as an operand. After the execution unit substantially completes the algorithm, the linear shift register shifts a new data value into the second data cell. In response to the linear shift register shifting new data into the second data cell, the execution unit re-performs the algorithm.

Abstract: A digital camera having a central processing unit with an embedded micro-code engine comprises a system memory capable of storing an instruction, at least one CPU execution unit electrically coupled with the system memory, and at least one micro-code engine electrically coupled with the CPU execution unit. The at least one CPU execution unit receive and decodes the instruction stored in the system memory. In response to the decoded instruction, the CPU execution unit sends commands and instruction parameters to at least one of an arithmetic logic unit of the CPU execution unit and the micro-code engine to execute the instruction. Typically the at least one CPU execution unit and the at least one micro-code engine operate in synchronization to execute the instruction.