Patents by Inventor Kang Seol Lee
Kang Seol Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10580480Abstract: A semiconductor memory apparatus includes a driving voltage providing circuit suitable for selectively providing a first driving voltage, a second driving voltage, a third driving voltage, a ground voltage, and a precharge voltage to a first driving line and a second driving line in response to an active signal, a cell characteristic information signal, and a precharge signal. The semiconductor memory apparatus also includes a sense amplifier suitable for operating by being applied with voltages provided from the first and second driving lines.Type: GrantFiled: June 14, 2019Date of Patent: March 3, 2020Assignee: SK hynix Inc.Inventors: Jung Hwan Lee, Dae Yong Shim, Kang Seol Lee
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Publication number: 20190295625Abstract: A semiconductor memory apparatus includes a driving voltage providing circuit suitable for selectively providing a first driving voltage, a second driving voltage, a third driving voltage, a ground voltage, and a precharge voltage to a first driving line and a second driving line in response to an active signal, a cell characteristic information signal, and a precharge signal. The semiconductor memory apparatus also includes a sense amplifier suitable for operating by being applied with voltages provided from the first and second driving lines.Type: ApplicationFiled: June 14, 2019Publication date: September 26, 2019Applicant: SK hynix Inc.Inventors: Jung Hwan LEE, Dae Yong SHIM, Kang Seol LEE
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Patent number: 10332585Abstract: A semiconductor memory apparatus includes a driving voltage providing circuit suitable for selectively providing a first driving voltage, a second driving voltage, a third driving voltage, a ground voltage, and a precharge voltage to a first driving line and a second driving line in response to an active signal, a cell characteristic information signal, and a precharge signal. The semiconductor memory apparatus also includes a sense amplifier suitable for operating by being applied with voltages provided from the first and second driving lines.Type: GrantFiled: August 24, 2017Date of Patent: June 25, 2019Assignee: SK hynix, Inc.Inventors: Jung Hwan Lee, Dae Yong Shim, Kang Seol Lee
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Patent number: 10290333Abstract: A semiconductor device includes an internal operation control circuit suitable for generating a set period signal which is enabled for a set period, in response to a write command and an internal operation control signal, and generating a column select signal, an output control signal and an input control signal in response to the set period signal; and an internal operation circuit suitable for performing an internal operation of converting parity data generated from input data and storing the converted parity data in a memory cell array, in response to the column select signal, the output control signal and the input control signal.Type: GrantFiled: June 2, 2017Date of Patent: May 14, 2019Assignee: SK hynix Inc.Inventors: Seol Hee Lee, Chang Hyun Kim, Dae Yong Shim, Kang Seol Lee
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Patent number: 10248427Abstract: A semiconductor device includes one or more internal circuits; a nonvolatile memory circuit including a first region suitable for storing first data for the nonvolatile memory circuit and a second region suitable for storing second data for the internal circuits; a first register suitable for temporarily storing the first data; one or more second registers suitable for temporarily storing the second data; and a control circuit suitable for controlling the nonvolatile memory circuit to transmit the first data and the second data to the first register and to the second registers, respectively, when a boot-up operation is performed.Type: GrantFiled: December 11, 2014Date of Patent: April 2, 2019Assignee: SK hynix Inc.Inventor: Kang-Seol Lee
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Publication number: 20180182447Abstract: A semiconductor memory apparatus includes a driving voltage providing circuit suitable for selectively providing a first driving voltage, a second driving voltage, a third driving voltage, a ground voltage, and a precharge voltage to a first driving line and a second driving line in response to an active signal, a cell characteristic information signal, and a precharge signal. The semiconductor memory apparatus also includes a sense amplifier suitable for operating by being applied with voltages provided from the first and second driving lines.Type: ApplicationFiled: August 24, 2017Publication date: June 28, 2018Applicant: SK hynix Inc.Inventors: Jung Hwan LEE, Dae Yong SHIM, Kang Seol LEE
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Patent number: 10008290Abstract: A repair control device for memory cells divided into a plurality of banks may include a failed address storage circuit configured to sort and store a plurality of failed addresses each containing a failed bank address and a failed row address, according to the failed row address, and store the failed row address by matching the failed row address with total failed bank information representing one or more failed banks indicated by the failed row address. The repair control device also includes an address comparison circuit configured to compare an input address to a pair comprised of the failed row address and the total failed bank information, stored in the failed address storage circuit, and generate a hit signal based on the comparison result. The repair control device further includes an address generation circuit configured to generate an access target address based on the hit signal.Type: GrantFiled: April 20, 2017Date of Patent: June 26, 2018Assignee: SK hynix Inc.Inventors: Seol Hee Lee, Kang Seol Lee
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Publication number: 20180130547Abstract: A repair control device for memory cells divided into a plurality of banks may include a failed address storage circuit configured to sort and store a plurality of failed addresses each containing a failed bank address and a failed row address, according to the failed row address, and store the failed row address by matching the failed row address with total failed bank information representing one or more failed banks indicated by the failed row address. The repair control device also includes an address comparison circuit configured to compare an input address to a pair comprised of the failed row address and the total failed bank information, stored in the failed address storage circuit, and generate a hit signal based on the comparison result. The repair control device further includes an address generation circuit configured to generate an access target address based on the hit signal.Type: ApplicationFiled: April 20, 2017Publication date: May 10, 2018Applicant: SK hynix Inc.Inventors: Seol Hee LEE, Kang Seol LEE
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Publication number: 20180068698Abstract: A semiconductor device includes an internal operation control circuit suitable for generating a set period signal which is enabled for a set period, in response to a write command and an internal operation control signal, and generating a column select signal, an output control signal and an input control signal in response to the set period signal; and an internal operation circuit suitable for performing an internal operation of converting parity data generated from input data and storing the converted parity data in a memory cell array, in response to the column select signal, the output control signal and the input control signal.Type: ApplicationFiled: June 2, 2017Publication date: March 8, 2018Applicant: SK hynix Inc.Inventors: Seol Hee LEE, Chang Hyun KIM, Dae Yong SHIM, Kang Seol LEE
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Patent number: 9607925Abstract: A semiconductor device may include: a plurality of output paths, which include a plurality of through silicon vias (TSVs), respectively, and suitable for transmission of test confirmation information; an information provider suitable for providing the test confirmation information to the plurality of TSVs; and an output controller suitable for selectively blocking one of the output paths including a failed one among the plurality of TSVs.Type: GrantFiled: September 16, 2014Date of Patent: March 28, 2017Assignee: SK Hynix Inc.Inventors: Tae-Sik Yun, Kang-Seol Lee
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Patent number: 9595529Abstract: A fuse cell circuit may include a bit line, a first fuse transistor having first and second program states, a first select transistor coupled between one terminal of the first fuse transistor and the bit line, and suitable for turning on when the first fuse transistor is selected, a second fuse transistor including one terminal coupled to the other terminal of the first fuse transistor, and having first and second program states, and a second select transistor coupled between a other terminal of the second fuse transistor and the bit line, and suitable for turning on when the second fuse transistor is selected.Type: GrantFiled: May 15, 2015Date of Patent: March 14, 2017Assignee: SK Hynix Inc.Inventor: Kang-Seol Lee
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Patent number: 9589603Abstract: A semiconductor device may include: a fuse array including a plurality of fuses; a voltage generation unit suitable for generating a first measurement voltage having a preset level; and a measurement unit suitable for supplying the first measurement voltage to a sourcing node of the fuse array and a second measurement voltage, which is provided from an external through a first pad, to a sinking node of the fuse array, and outputting a current, which is caused by voltage difference between the first and second measurement voltages and passes through one or more of the multiple fuses, through the first pad.Type: GrantFiled: August 15, 2014Date of Patent: March 7, 2017Assignee: SK Hynix Inc.Inventor: Kang-Seol Lee
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Patent number: 9489147Abstract: A memory device includes a memory array suitable for storing write data of the memory device and providing the stored data as read data of the memory device, a programmable storage unit suitable for storing information for the memory device, a command decoder suitable for storing decoding one or more command signals, and generating a write command for writing the write data, a read command for outputting the read data, and an information read command for outputting information stored in the programmable storage unit, a control unit suitable for controlling the information stored in the programmable storage unit to be sequentially read in response to activation of the information read command, and an output unit suitable for outputting the read information to an outside of the memory device in response to the information read command.Type: GrantFiled: December 16, 2013Date of Patent: November 8, 2016Assignee: SK Hynix Inc.Inventors: Kang-Seol Lee, Woo-Sik Jeong, Chun-Seok Jeong
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Patent number: 9437259Abstract: A memory may include first to Nth cell arrays configured to include a plurality of memory cells and one or more first to Nth data input/output pads respectively corresponding to the first to Nth cell arrays, wherein the one or more first to Nth data input/output pads are configured to input/output data to/from the first to Nth cell arrays.Type: GrantFiled: September 17, 2015Date of Patent: September 6, 2016Assignee: SK Hynix Inc.Inventors: Heat-Bit Park, Kang-Seol Lee
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Publication number: 20160181260Abstract: A fuse cell circuit may include a bit line, a first fuse transistor having first and second program states, a first select transistor coupled between one terminal of the first fuse transistor and the bit line, and suitable for turning on when the first fuse transistor is selected, a second fuse transistor including one terminal coupled to the other terminal of the first fuse transistor, and having first and second program states, and a second select transistor coupled between a other terminal of the second fuse transistor and the bit line, and suitable for turning on when the second fuse transistor is s elected.Type: ApplicationFiled: May 15, 2015Publication date: June 23, 2016Inventor: Kang-Seol LEE
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Patent number: 9337849Abstract: A phase detector includes a phase comparing circuit configured to detect and output a phase difference between a first clock signal and a second clock signal, a latch circuit configured to latch an output signal of the phase comparing circuit and output a phase detection signal, and an initial voltage control circuit configured to control an initial voltage of an input terminal of the latch circuit according to a control signal.Type: GrantFiled: July 7, 2014Date of Patent: May 10, 2016Assignees: SK HYNIX INC., INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITYInventors: Young-Hoon Kim, Soo-Young Jang, Chang-Sik Yoo, Chun-Seok Jeong, Kang-Seol Lee
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Publication number: 20160026471Abstract: A semiconductor device includes one or more internal circuits; a nonvolatile memory circuit including a first region suitable for storing first data for the nonvolatile memory circuit and a second region suitable for storing second data for the internal circuits; a first register suitable for temporarily storing the first data; one or more second registers suitable for temporarily storing the second data; and a control circuit suitable for controlling the nonvolatile memory circuit to transmit the first data and the second data to the first register and to the second registers, respectively, when a boot-up operation is performed.Type: ApplicationFiled: December 11, 2014Publication date: January 28, 2016Inventor: Kang-Seol LEE
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Patent number: 9236295Abstract: Provided is a semiconductor apparatus in which a plurality of semiconductor chips stacked in a vertical direction. Each of the semiconductor chips comprises: a bank area comprising a plurality of banks configured to store data; and a peripheral area including a pad area in which a plurality of pads configured to receive signals for controlling the bank area and a plurality of TSV for electrically connecting the plurality of pads, respectively.Type: GrantFiled: August 29, 2013Date of Patent: January 12, 2016Assignee: SK Hynix Inc.Inventors: Young Hee Yoon, Kang Seol Lee
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Publication number: 20160005443Abstract: A memory may include first to Nth cell arrays configured to include a plurality of memory cells and one or more first to Nth data input/output pads respectively corresponding to the first to Nth cell arrays, wherein the one or more first to Nth data input/output pads are configured to input/output data to/from the first to Nth cell arrays.Type: ApplicationFiled: September 17, 2015Publication date: January 7, 2016Inventors: Heat-Bit PARK, Kang-Seol LEE
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Patent number: 9165614Abstract: A memory may include first to Nth cell arrays configured to include a plurality of memory cells and one or more first to Nth data input/output pads respectively corresponding to the first to Nth cell arrays, wherein the one or more first to Nth data input/output pads are configured to input/output data to/from the first to Nth cell arrays.Type: GrantFiled: October 9, 2013Date of Patent: October 20, 2015Assignee: SK Hynix Inc.Inventors: Heat-Bit Park, Kang-Seol Lee