Abstract: In one embodiment, a integrated circuit (IC) configurable to have any one of a plurality of different feature sets, the IC including (a) one or more feature blocks adapted to be independently enabled or disabled, (b) a one-time-programmable (OTP) memory cell for each feature block, the OTP memory cell storing a value, and (c) a feature control module for each feature block, each feature control module connected between the corresponding OTP memory cell and the corresponding feature block, and adapted to enable or disable the corresponding feature block based on the value stored in the corresponding OTP memory cell. The OTP memory cells are programmed by a vendor to select the particular feature set for the IC which is to be available to a purchaser.

Abstract: In one embodiment, the invention is an integrated circuit (IC) including an OTP memory and conditioning circuitry. The IC receives an externally-generated DC programming voltage signal that the conditioning circuitry transforms into a programming pulse signal for programming the OTP memory. The conditioning circuitry includes: (i) reset protection circuitry for holding the programming pulse signal low if the IC is powering up, (ii) an overvoltage protection circuit for substantially preventing the programming pulse voltage from exceeding predefined boundaries, and (iii) a conversion switch for controlling the programming pulse voltage. The programming pulse voltage is (i) substantially equivalent to the externally-generated DC voltage if an enable signal is on, and (ii) substantially equivalent to a reference voltage if the enable signal is off.

Abstract: An OTP and Reset Assert Counter and a method for protecting one-time programmable memory settings during read-out from an OTP memory block. The OTP memory block is set at ground and in a reset mode with a clock driven External Reset (RSTB) signal set at ground true active. A Delay Counter is programmed with a time delay to correspond with the time that is inherently needed by the OTP Memory block to complete a read-out process that begins with the External Reset (RSTB) signal being set to HIGH; and an input Clock signal is delayed by the Delay Counter for a duration of the time delay that begins with the External Reset (RSTB) signal being set to HIGH.

Abstract: In one embodiment, a integrated circuit (IC) configurable to have any one of a plurality of different feature sets, the IC including (a) one or more feature blocks adapted to be independently enabled or disabled, (b) a one-time-programmable (OTP) memory cell for each feature block, the OTP memory cell storing a value, and (c) a feature control module for each feature block, each feature control module connected between the corresponding OTP memory cell and the corresponding feature block, and adapted to enable or disable the corresponding feature block based on the value stored in the corresponding OTP memory cell. The OTP memory cells are programmed by a vendor to select the particular feature set for the IC which is to be available to a purchaser.

Abstract: In one embodiment, a integrated circuit (IC) configurable to have any one of a plurality of different feature sets, the IC including (a) one or more feature blocks adapted to be independently enabled or disabled, (b) a one-time-programmable (OTP) memory cell for each feature block, the OTP memory cell storing a value, and (c) a feature control module for each feature block, each feature control module connected between the corresponding OTP memory cell and the corresponding feature block, and adapted to enable or disable the corresponding feature block based on the value stored in the corresponding OTP memory cell. The OTP memory cells are programmed by a vendor to select the particular feature set for the IC which is to be available to a purchaser.

Abstract: In one embodiment, a integrated circuit (IC) configurable to have any one of a plurality of different feature sets, the IC including (a) one or more feature blocks adapted to be independently enabled or disabled, (b) a one-time-programmable (OTP) memory cell for each feature block, the OTP memory cell storing a value, and (c) a feature control module for each feature block, each feature control module connected between the corresponding OTP memory cell and the corresponding feature block, and adapted to enable or disable the corresponding feature block based on the value stored in the corresponding OTP memory cell. The OTP memory cells are programmed by a vendor to select the particular feature set for the IC which is to be available to a purchaser.

Abstract: In one embodiment, the invention is an integrated circuit (IC) including an OTP memory and conditioning circuitry. The IC receives an externally-generated DC programming voltage signal that the conditioning circuitry transforms into a programming pulse signal for programming the OTP memory. The conditioning circuitry includes: (i) reset protection circuitry for holding the programming pulse signal low if the IC is powering up, (ii) an overvoltage protection circuit for substantially preventing the programming pulse voltage from exceeding predefined boundaries, and (iii) a conversion switch for controlling the programming pulse voltage. The programming pulse voltage is (i) substantially equivalent to the externally-generated DC voltage if an enable signal is on, and (ii) substantially equivalent to a reference voltage if the enable signal is off.

Abstract: Each column in the memory array of transistors of a programmable read only memory (ROM) can be programmed in either a conventional mode or an inverted mode. In the conventional mode, each transistor is either programmed (i.e., connected to the corresponding bit line) or unprogrammed (i.e., left unconnected to the corresponding bit line). In this way, the programming mode can be selected, independently for each column, to limit the maximum number of transistors that can be programmed in any given column to one half of the total number of transistors in the column. As such, the total capacitance along a bit line is reduced and the access time is therefore also reduced, resulting in a faster ROM. The information as to which columns are encoded using which programming modes is contained in a component of the ROM. That programming-mode information is accessed when reading data out of the memory array to determine whether or not to invert the data for the various columns.

Abstract: An integrated circuit memory array includes column conductors that are precharged during a precharge period in order to reduce the effects of power supply voltage variations, a load resistor is connected between the column conductors and ground during a portion of the precharge period. In this manner, a voltage-divider is formed that provides a discharge path which prevents over-charging of the column conductors. An increase in power supply noise immunity is gained, thereby avoiding degradation of the worst-case memory access time that could otherwise occurs.

Abstract: A monolithic integrated circuit memory control operating through the use of MOS field-effect transistors with diode or bipolar circuit arrangement for the bit line column switching.

Abstract: An OR logic function is provided in at least two separate circuit branches by diodes in parallel summing current at a first logic node and a first circuit branch and diodes in parallel summing current at a second logic node in a second current branch. An AND logic function is performed at a third logic node by using additional diodes connected in parallel at the third logic node so as to share current passing through the third logic node, with the logic conditions at the first and second logic nodes serving as the inputs to the AND logic function. The logic condition at the third logic node is applied to the gate of a switching FET. The switching FET is conveniently employed to invert the logic condition at the third logic node. The invention is particularly suited for use with MESFET logic families using gallium arsenide (GaAs) substrates.

Abstract: An IMPATT oscillator is thermally stabilized for pulsed operation by utilizing the dissipative heat during subperiods of pulsed operation and a variable self-heating due to a bias voltage applied during non-oscillating subperiods. The oscillator comprises an IMPATT diode mounted on a platform which is attached to a housing defining a resonating cavity. The platform has a thermally insulating base with a layer of thermally and electrically conducting material applied thereon. The thickness of the layer of thermally and electrically conducting material must be sufficient to permit microwave resonances to occur within the cavity. The thermal resistance of the layer is selected to permit the junction temperature to remain constant even for the highest ambient temperature condition. Constant junction temperature over a wide range of ambient temperature produces constant power and frequency characteristics.