Abstract: A method of driving an electronic device includes displaying a plurality of fingerprint recognition icons on a display device configured to perform fingerprint recognition, and releasing a lock state of the display device through a fingerprint authentication process upon determining at least one first fingerprint recognition icon among the plurality of fingerprint recognition icons is touched. The plurality of fingerprint recognition icons include at least one first fingerprint recognition icon configured to support the fingerprint recognition and at least one second fingerprint recognition icon configured to not support the fingerprint recognition.

Abstract: A water-cooled heat dissipation module assembly capable of cooling a power module of a vehicle driving inverter system using a battery or fuel cell. The water-cooled heat dissipation module assembly includes a housing unit provided in the form of a housing having an opening portion at least partially opened at one side thereof. The housing unit and at least a part of a rim region of the cooling unit are made of a plastic material, and the housing unit and the cooling unit are joined to each other by plastic welding using a laser.

Abstract: A display includes: a display panel; and a panel bottom sheet disposed below the display panel, the panel bottom sheet including: a first heat dissipation layer; a second heat dissipation layer over the first heat dissipation layer, including a first opening formed completely through the second heat dissipation layer in a thickness direction; a heat dissipation coupling interlayer between the first heat dissipation layer and the second heat dissipation layer, and a heat dissipation substrate on the second heat dissipation layer.

Abstract: A positive electrode active material for a lithium secondary battery has a mixture of microparticles having a predetermined average particle size (D50) and macroparticles having a larger average particle size (D50) than the microparticles. The microparticles have the average particle size (D50) of 1 to 10 ?m and are at least one selected from the group consisting of particles having a carbon material coating layer on all or part of a surface of primary macroparticles having an average particle size (D50) of 1 ?m or more, particles having a carbon material coating layer on all or part of a surface of secondary particles formed by agglomeration of the primary macroparticles, and a mixture thereof. The macroparticles are secondary particles having an average particle size (D50) of 5 to 20 ?m formed by agglomeration of primary microparticles having a smaller average particle size (D50) than the primary macroparticles.

Abstract: A display device including: a substrate; an active layer disposed on the substrate and including active patterns; a first conductive layer disposed on the active layer; a second conductive layer disposed on the first conductive layer and including a data line; a third conductive layer disposed on the second conductive layer; and a light-emitting element disposed on the third conductive layer, wherein the first conductive layer includes a scan line, a first voltage line, and a second voltage line, the third conductive layer includes a third voltage line connected to the first voltage line and a fourth voltage line connected to the second voltage line, the first voltage line and the second voltage line extend in a first direction, the third voltage line and the fourth voltage line extend in a second direction, and the third voltage line and the fourth voltage line are alternately arranged in the first direction.

Abstract: A memory device including a plurality of memory cells, a peripheral circuit, and a control logic. The peripheral circuit performs a first read operation using a plurality of read voltages on selected memory cells. The control logic controls the peripheral circuit to perform a cell counting operation, adjust remaining read voltages among the plurality of read voltages based on a read offset table and a cell count which is a result of the cell counting operation, and perform a first read operation on the selected memory cell with the remaining read voltages, in the first read operation. The control logic performs a read data output operation of a second read operation performed before the first read operation and the cell counting operation corresponding to the first read operation in parallel among a plurality of successively performed read operations.

Abstract: A memory device includes a memory group comprising plural memory cells, a control circuitry configured to read a first hard decision data entry and a first soft decision data entry together from a first memory cell among the plural memory cells, and a page buffer circuit, coupled to the first memory cell via a bit line. The page buffer circuit includes plural data latches configured to store the first hard decision data entry and the first soft decision data entry and at least one cache latch configured to store one of the first hard decision data entry and the first soft decision data entry which are transferred from the plural data latches.

Abstract: A memory device including a plurality of memory cells, a peripheral circuit, and a control logic. The peripheral circuit performs a first read operation using a plurality of read voltages on selected memory cells. The control logic controls the peripheral circuit to perform a cell counting operation, adjust remaining read voltages among the plurality of read voltages based on a read offset table and a cell count which is a result of the cell counting operation, and perform a first read operation on the selected memory cell with the remaining read voltages, in the first read operation. The control logic performs a read data output operation of a second read operation performed before the first read operation and the cell counting operation corresponding to the first read operation in parallel among a plurality of successively performed read operations.

Abstract: The present technology relates to a page buffer and a semiconductor memory device including the page buffer. The page buffer includes a first latch circuit configured to store data corresponding to one of a first program state and a second program state, a bit line controller connected to a bit line of a memory block and precharging the bit line by applying one of a first set voltage and a second set voltage to the bit line according to the data stored in the first latch circuit during a bit line precharge operation in a program verify operation, and a second latch circuit connected to the bit line controller through a main sensing node and configured to sense first verify data according to a potential level of the main sensing node during the program verify operation.

Abstract: Provided herein may be a page buffer and a semiconductor memory device having the same. The page buffer may include a sensing node, of which a potential is controlled based on an amount of current flowing through a bit line during a data sensing operation and based on a potential of a page buffer common node during a data transmission operation, and a main latch component configured to latch data based on the potential of the sensing node, wherein the main latch component latches the data depending on a first trip voltage and the potential of the sensing node during the data transmission operation, and latches the data depending on a second trip voltage and the potential of the sensing node during the data sensing operation, the first trip voltage and the second trip voltage being different.

Abstract: Provided herein may be a page buffer and a semiconductor memory device having the same. The page buffer may include a sensing node, of which a potential is controlled based on an amount of current flowing through a bit line during a data sensing operation and based on a potential of a page buffer common node during a data transmission operation, and a main latch component configured to latch data based on the potential of the sensing node, wherein the main latch component latches the data depending on a first trip voltage and the potential of the sensing node during the data transmission operation, and latches the data depending on a second trip voltage and the potential of the sensing node during the data sensing operation, the first trip voltage and the second trip voltage being different.

Abstract: The present technology relates to a page buffer and a semiconductor memory device including the page buffer. The page buffer includes a first latch circuit configured to store data corresponding to one of a first program state and a second program state, a bit line controller connected to a bit line of a memory block and precharging the bit line by applying one of a first set voltage and a second set voltage to the bit line according to the data stored in the first latch circuit during a bit line precharge operation in a program verify operation, and a second latch circuit connected to the bit line controller through a main sensing node and configured to sense first verify data according to a potential level of the main sensing node during the program verify operation.

Abstract: A data transfer training method includes determining whether a program data transfer training command or a read data transfer training command is received from a host device; transferring normal program signals to non-training memory devices among a plurality of memory devices and performing a program data transfer training to a training memory device among a plurality of memory devices while performing normal program operations to the non-training memory devices in response to a received program data transfer training command; and transferring normal read signals to the non-training memory devices, and performing a read data transfer training to the training memory device while performing normal read operations to the non-training memory devices in response to a received read data transfer training command.

Abstract: The present disclosure relates to an apparatus and method of allocating a question according to a question type or question feature. A question allocating apparatus for the same may include a question analysis unit generating at least one of question type information and question feature information of a current question; and a question allocating unit determining an answer generating unit suitable for the current questions among a plurality of answer generating units based on at least one of the question type information, and the question feature information, and allocating the current question to at least one answer generating including the determined answer generating unit.

Abstract: A data transfer training method includes determining whether a program data transfer training command or a read data transfer training command is received from a host device; transferring normal program signals to non-training memory devices among a plurality of memory devices and performing a program data transfer training to a training memory device among a plurality of memory devices while performing normal program operations to the non-training memory devices in response to a received program data transfer training command; and transferring normal read signals to the non-training memory devices, and performing a read data transfer training to the training memory device while performing normal read operations to the non-training memory devices in response to a received read data transfer training command.

Abstract: A non-volatile memory device includes: a plurality of cache latches; a pair of input/output lines; a plurality of switches, each couples a corresponding cache latch to the pair of the input/output lines, when the corresponding cache latch is selected among the plurality of cache latches; a pre-charger suitable for pre-charging the pair of the input/output lines; and a sense-amplifier suitable for sensing and amplifying the data of the pair of the input/output lines, wherein the sense-amplifier operates with a first power source voltage, and the plurality of the cache latches, the plurality of the switches, and the pre-charger operate with a second power source voltage having a voltage level that is higher than the voltage level of the first power source voltage.

Abstract: A semiconductor memory apparatus may include a memory cell circuit, a data latch circuit, and a first stage amplification circuit. The data latch circuit may be electrically coupled to the memory cell circuit by a bit line. The data latch circuit may latch data transferred through the bit line. The data latch circuit may output latched data to an input/output line in response to a cell select signal. The data first stage amplification circuit may generate driving data to a voltage level of an external power supply voltage in response to a voltage level of the input/output line. The data first stage amplification circuit may precharge the input/output line to a voltage level lower than the external power supply voltage and higher than a ground voltage in response to a precharge signal.

Abstract: A non-volatile memory device includes: a plurality of cache latches; a pair of input/output lines; a plurality of switches, each couples a corresponding cache latch to the pair of the input/output lines, when the corresponding cache latch is selected among the plurality of cache latches; a pre-charger suitable for pre-charging the pair of the input/output lines; and a sense-amplifier suitable for sensing and amplifying the data of the pair of the input/output lines, wherein the sense-amplifier operates with a first power source voltage, and the plurality of the cache latches, the plurality of the switches, and the pre-charger operate with a second power source voltage having a voltage level that is higher than the voltage level of the first power source voltage.

Abstract: A semiconductor memory apparatus may include a memory cell circuit, a data latch circuit, and a first stage amplification circuit. The data latch circuit may be electrically coupled to the memory cell circuit by a bit line. The data latch circuit may latch data transferred through the bit line. The data latch circuit may output latched data to an input/output line in response to a cell select signal. The data first stage amplification circuit may generate driving data to a voltage level of an external power supply voltage in response to a voltage level of the input/output line. The data first stage amplification circuit may precharge the input/output line to a voltage level lower than the external power supply voltage and higher than a ground voltage in response to a precharge signal.

Abstract: A sense amplifier includes a first input circuit, a second input circuit and an amplification circuit. The first input circuit may receive a pair of first input signals and change voltage levels of amplification nodes. The second input circuit may receive a pair of second input signals and change voltage levels of the amplification nodes. The amplification circuit may receive a first voltage, amplify voltage level changes of the amplification nodes, and output a pair of output signals through output nodes.