Abstract: A water-cooled heat dissipation module assembly capable of cooling a power module of a vehicle driving inverter system using a battery or fuel cell. The water-cooled heat dissipation module assembly includes a housing unit provided in the form of a housing having an opening portion at least partially opened at one side thereof. The housing unit and at least a part of a rim region of the cooling unit are made of a plastic material, and the housing unit and the cooling unit are joined to each other by plastic welding using a laser.

Abstract: A display device including a substrate, a first upper power line, a conductive member, a protective insulating layer, an upper connection member, and a sub-pixel structure. The upper connection member is disposed in a first pad area and a first peripheral area on a planarization layer, and electrically connects the first upper power line and the conductive member through a first contact hole, which is formed in the protective insulating layer and the planarization layer located on the conductive member, and a second contact hole, which is formed in the protective insulating layer and the planarization layer located on the first upper power line.

Abstract: An organic light emitting diode display includes a clock wiring circuit including a first signal line and a second signal line, a resistance adjusting circuit including a first lower resistance line and a first upper resistance line connected to the first signal line and a second lower resistance line and a second upper resistance line connected to the second signal line, and a gate driving circuit connected to the resistance adjusting circuit. The second signal line is disposed closer to the gate driving circuit than the first signal line, the first lower resistance line and the second lower resistance line have higher resistivity than the first upper resistance line and the second upper resistance line, respectively, the first lower resistance line is shorter than the second lower resistance line, and the first upper resistance line is longer than the second upper resistance line.

Abstract: Provided herein are a memory system and a method of programming the same. The memory system may include a memory device including memory cells for storing data and a plurality of latches for storing code values indicating the data. The memory device may be configured to program data into each of the memory cells, store an original code value indicating the data in the plurality of latches, and change the original code value stored in the plurality of latches to an erase code value in response to a verification pass, and a memory controller configured to output, to the memory device, a suspend command for suspending at least the programming in response to detecting a sudden power-off and a recovery command for restoring a code value changed to the erase code value.

Abstract: A memory device includes a memory group comprising plural memory cells, a control circuitry configured to read a first hard decision data entry and a first soft decision data entry together from a first memory cell among the plural memory cells, and a page buffer circuit, coupled to the first memory cell via a bit line. The page buffer circuit includes plural data latches configured to store the first hard decision data entry and the first soft decision data entry and at least one cache latch configured to store one of the first hard decision data entry and the first soft decision data entry which are transferred from the plural data latches.

Abstract: Provided herein may be a semiconductor memory device. The semiconductor memory device may include a memory cell array including a plurality of memory cells, a plurality of page buffers respectively coupled to the plurality of memory cells through bit lines, and a control logic configured to control a program operation of each of the plurality of page buffers. Each of the plurality of page buffers may include a first latch circuit configured to store first data indicating a main verification result obtained using a main verify voltage, a second latch circuit configured to store second data indicating a first sub-verification result obtained using a first sub-verify voltage lower than the main verify voltage, and a third latch circuit configured to store third data indicating a second sub-verification result obtained using a second sub-verify voltage lower than the first sub-verify voltage.

Abstract: A memory device including a page buffer is part of a memory system. The memory device includes first memory cells, each configured to be programmed to have a threshold voltage corresponding to any one of a plurality of program states. The memory device also includes data latches configured to respectively store a plurality of pieces of first logical page data to be stored in the first memory cells. The memory device further includes a pre-sensing latch configured to store data sensed through a pre-verify operation. The pre-sensing latch stores second logical page data to be stored in second memory cells when a main verify operation for a threshold program state, among the plurality of program states, has passed.

Abstract: A memory device including a plurality of memory cells, a peripheral circuit, and a control logic. The peripheral circuit performs a first read operation using a plurality of read voltages on selected memory cells. The control logic controls the peripheral circuit to perform a cell counting operation, adjust remaining read voltages among the plurality of read voltages based on a read offset table and a cell count which is a result of the cell counting operation, and perform a first read operation on the selected memory cell with the remaining read voltages, in the first read operation. The control logic performs a read data output operation of a second read operation performed before the first read operation and the cell counting operation corresponding to the first read operation in parallel among a plurality of successively performed read operations.

Abstract: A memory device includes a memory group comprising plural memory cells, a control circuitry configured to read a first hard decision data entry and a first soft decision data entry together from a first memory cell among the plural memory cells, and a page buffer circuit, coupled to the first memory cell via a bit line. The page buffer circuit includes plural data latches configured to store the first hard decision data entry and the first soft decision data entry and at least one cache latch configured to store one of the first hard decision data entry and the first soft decision data entry which are transferred from the plural data latches.

Abstract: A memory device including a plurality of memory cells, a peripheral circuit, and a control logic. The peripheral circuit performs a first read operation using a plurality of read voltages on selected memory cells. The control logic controls the peripheral circuit to perform a cell counting operation, adjust remaining read voltages among the plurality of read voltages based on a read offset table and a cell count which is a result of the cell counting operation, and perform a first read operation on the selected memory cell with the remaining read voltages, in the first read operation. The control logic performs a read data output operation of a second read operation performed before the first read operation and the cell counting operation corresponding to the first read operation in parallel among a plurality of successively performed read operations.

Abstract: The present technology relates to a page buffer and a semiconductor memory device including the page buffer. The page buffer includes a first latch circuit configured to store data corresponding to one of a first program state and a second program state, a bit line controller connected to a bit line of a memory block and precharging the bit line by applying one of a first set voltage and a second set voltage to the bit line according to the data stored in the first latch circuit during a bit line precharge operation in a program verify operation, and a second latch circuit connected to the bit line controller through a main sensing node and configured to sense first verify data according to a potential level of the main sensing node during the program verify operation.

Abstract: Provided herein may be a page buffer and a semiconductor memory device having the same. The page buffer may include a sensing node, of which a potential is controlled based on an amount of current flowing through a bit line during a data sensing operation and based on a potential of a page buffer common node during a data transmission operation, and a main latch component configured to latch data based on the potential of the sensing node, wherein the main latch component latches the data depending on a first trip voltage and the potential of the sensing node during the data transmission operation, and latches the data depending on a second trip voltage and the potential of the sensing node during the data sensing operation, the first trip voltage and the second trip voltage being different.

Abstract: Provided herein may be a page buffer and a semiconductor memory device having the same. The page buffer may include a sensing node, of which a potential is controlled based on an amount of current flowing through a bit line during a data sensing operation and based on a potential of a page buffer common node during a data transmission operation, and a main latch component configured to latch data based on the potential of the sensing node, wherein the main latch component latches the data depending on a first trip voltage and the potential of the sensing node during the data transmission operation, and latches the data depending on a second trip voltage and the potential of the sensing node during the data sensing operation, the first trip voltage and the second trip voltage being different.

Abstract: The present technology relates to a page buffer and a semiconductor memory device including the page buffer. The page buffer includes a first latch circuit configured to store data corresponding to one of a first program state and a second program state, a bit line controller connected to a bit line of a memory block and precharging the bit line by applying one of a first set voltage and a second set voltage to the bit line according to the data stored in the first latch circuit during a bit line precharge operation in a program verify operation, and a second latch circuit connected to the bit line controller through a main sensing node and configured to sense first verify data according to a potential level of the main sensing node during the program verify operation.

Abstract: A data transfer training method includes determining whether a program data transfer training command or a read data transfer training command is received from a host device; transferring normal program signals to non-training memory devices among a plurality of memory devices and performing a program data transfer training to a training memory device among a plurality of memory devices while performing normal program operations to the non-training memory devices in response to a received program data transfer training command; and transferring normal read signals to the non-training memory devices, and performing a read data transfer training to the training memory device while performing normal read operations to the non-training memory devices in response to a received read data transfer training command.

Abstract: The present disclosure relates to an apparatus and method of allocating a question according to a question type or question feature. A question allocating apparatus for the same may include a question analysis unit generating at least one of question type information and question feature information of a current question; and a question allocating unit determining an answer generating unit suitable for the current questions among a plurality of answer generating units based on at least one of the question type information, and the question feature information, and allocating the current question to at least one answer generating including the determined answer generating unit.

Abstract: A data transfer training method includes determining whether a program data transfer training command or a read data transfer training command is received from a host device; transferring normal program signals to non-training memory devices among a plurality of memory devices and performing a program data transfer training to a training memory device among a plurality of memory devices while performing normal program operations to the non-training memory devices in response to a received program data transfer training command; and transferring normal read signals to the non-training memory devices, and performing a read data transfer training to the training memory device while performing normal read operations to the non-training memory devices in response to a received read data transfer training command.

Abstract: A non-volatile memory device includes: a plurality of cache latches; a pair of input/output lines; a plurality of switches, each couples a corresponding cache latch to the pair of the input/output lines, when the corresponding cache latch is selected among the plurality of cache latches; a pre-charger suitable for pre-charging the pair of the input/output lines; and a sense-amplifier suitable for sensing and amplifying the data of the pair of the input/output lines, wherein the sense-amplifier operates with a first power source voltage, and the plurality of the cache latches, the plurality of the switches, and the pre-charger operate with a second power source voltage having a voltage level that is higher than the voltage level of the first power source voltage.

Abstract: A semiconductor memory apparatus may include a memory cell circuit, a data latch circuit, and a first stage amplification circuit. The data latch circuit may be electrically coupled to the memory cell circuit by a bit line. The data latch circuit may latch data transferred through the bit line. The data latch circuit may output latched data to an input/output line in response to a cell select signal. The data first stage amplification circuit may generate driving data to a voltage level of an external power supply voltage in response to a voltage level of the input/output line. The data first stage amplification circuit may precharge the input/output line to a voltage level lower than the external power supply voltage and higher than a ground voltage in response to a precharge signal.

Abstract: A semiconductor memory apparatus may include a memory cell circuit, a data latch circuit, and a first stage amplification circuit. The data latch circuit may be electrically coupled to the memory cell circuit by a bit line. The data latch circuit may latch data transferred through the bit line. The data latch circuit may output latched data to an input/output line in response to a cell select signal. The data first stage amplification circuit may generate driving data to a voltage level of an external power supply voltage in response to a voltage level of the input/output line. The data first stage amplification circuit may precharge the input/output line to a voltage level lower than the external power supply voltage and higher than a ground voltage in response to a precharge signal.