Abstract: A delay lock loop having improved timing control of input signals. Specifically, a fine delay block is provided having feedback loops therein such that the fine delay block is self tuning. The output of the fine delay block may be implemented to control a coarse delay block in a delay lock loop.

Abstract: A delay lock loop having improved timing control of input signals. Specifically, a fine delay block is provided having feedback loops therein such that the fine delay block is self tuning. The output of the fine delay block may be implemented to control a coarse delay block in a delay lock loop.

Abstract: A delay lock loop having improved timing control of input signals. Specifically, a fine delay block is provided having feedback loops therein such that the fine delay block is self tuning. The output of the fine delay block may be implemented to control a coarse delay block in a delay lock loop.

Abstract: One delay locked loop circuit embodiment includes a delay line system configured to generate a clock output signal by adding a delay line system time delay to a clock reference signal, a phase detector, a shift register, and a control unit. The delay line system includes a coarse delay line to adjust the delay line system time delay by remote coarse-shifting, a phase selector configured to adjust the delay line system time delay by local coarse-shifting output signals from a series of local coarse delay units, and a phase mixer to adjust a particular time delay of the clock output signal by fine-shifting. The phase mixer does not receive the clock reference signal. The phase detector detects a phase difference between the clock reference signal and the clock output signal. The shift register controls the remote coarse-shifting, and the control unit controls the local coarse-shifting, based on the phase difference.

Abstract: Methods, circuits, devices, and systems are provided, including embodiments with local coarse delay units. One embodiment includes generating a first delayed signal, a second delayed signal, and a third delayed signal by delaying a clock reference signal with various time delays of a coarse delay line and local coarse delay units. This method embodiment also includes generating a clock output signal based on the first delayed signal, the second delayed signal, or the third delayed signal, depending on a phase difference between the clock reference signal and the clock output signal.

Abstract: A device and system having improved timing control of input signals. Specifically, a fine delay block is provided having feedback loops therein such that the fine delay block is self tuning. The output of the fine delay block may be implemented to control a coarse delay block in a delay lock loop.

Abstract: Methods, circuits, devices, and systems are provided, including embodiments with local coarse delay units. One embodiment includes generating a first delayed signal, a second delayed signal, and a third delayed signal by delaying a clock reference signal with various time delays of a coarse delay line and local coarse delay units. This method embodiment also includes generating a clock output signal based on the first delayed signal, the second delayed signal, or the third delayed signal, depending on a phase difference between the clock reference signal and the clock output signal.

Abstract: A device and system having improved timing control of input signals. Specifically, a fine delay block is provided having feedback loops therein such that the fine delay block is self tuning. The output of the fine delay block may be implemented to control a coarse delay block in a delay lock loop.