Abstract: A semiconductor device and method of manufacturing the device that includes a growth die and a dummy die. The method includes patterning, on an integrated circuit wafer, at one least growth die, and patterning at least one dummy die that is positioned on at least a portion of a circumference of the integrated circuit wafer. The patterned growth and dummy dies are etched on the wafer. A bond wave is initiated at a starting point on the integrated circuit wafer. The starting point is positioned on an edge of the integrated circuit wafer opposite the portion on which the at least one dummy die is patterned. Upon application of pressure at the starting point, a uniform bond wave propagates across the wafers, bonding the two wafers together.

Abstract: A method of manufacturing a semiconductor device includes forming a conductive layer over a first substrate, forming at least one circuit element at least partially from a semiconductor material of a second substrate, bonding the first substrate to the second substrate, etching a through via extending through the second substrate to partially expose the conductive layer, depositing at least one conductive material in the through via to form a conductive through via electrically coupled to the conductive layer and over the second substrate to form a first contact structure electrically coupling the conductive through via to the at least one circuit element. The at least one circuit element includes at least one of a Schottky diode, a capacitor, or a resistor.

Abstract: A semiconductor device and method of manufacturing the device that includes a capacitive micromachined ultrasonic transducer (CMUT). The CMUT includes an integrated circuit substrate, and a sensing electrode positioned on the integrated substrate. The sensing electrode includes a sidewall that forms a wall of an isolation trench adjacent to the sensing electrode, and is patterned before covering dielectric layers are deposited. After patterning of the sensing electrode, one or more dielectric layers are patterned, with one dielectric layer patterned on the sensing electrode and sidewall, and which has a thickness corresponding to the surface roughness of the sensing electrode. The CMUT further includes a membrane positioned above the sensing electrode forming a cavity therein.

Abstract: The present disclosure provides a magnetic composite material composition, a magnetic core for an inductor and a manufacturing method therefor. It includes a magnetically soft alloy, a thermosetting resin, a curing agent, and an organic solvent. The organic solvent contains at least two types of volatile solvents, and a difference between boiling points of the volatile solvents ranges from 100 to 170° C. The magnetically soft alloy and the thermosetting resin may be cured and formed under the action of the curing agent. The magnetic composite material of the above composition has good high-temperature resistance. Different types of the volatile solvents may be successively volatilized rather than rapidly volatilized at one time as the curing reaction undergoes. Therefore, a large amount of pores can be prevented from being produced on the surface and internal of the magnetic composite material composition, thereby enhancing the compactness and relative permeability.

Abstract: Disclosed are a fully-integrated voltage regulation module inductor magnetic slurry and a preparation method thereof; in parts by mass, the components of the magnetic slurry comprise: 100 parts of a soft magnetic alloy powder, 9-13 parts of a binder and 2.85-4.61 parts of a curing agent; wherein the binder comprises bisphenol F epoxy resin and an aromatic reactive diluent; and the preparation method utilizes mechanical stirring and vacuum defoaming treatment to obtain a magnetic slurry having a suitable viscosity and good high-temperature resistance performance. The preparation method of the present application is simple in operation, has low preparation costs and is suitable for industrial manufacture.

Abstract: Provided in the present application are a power inductor and a preparation method therefor. The preparation method comprises the process steps of slurry preparation, slurry casting, coil winding, coil arrangement, slurry pouring, warm-water pressing, curing treatment, UV adhesive film lamination, cutting, etc. A small-size power inductor can be simply and efficiently prepared, the preparation method is particularly suitable for ultrathin inductors, the phenomena of a short circuit, an open circuit, etc., appearing due to the damage to copper wires that is caused by using dry-pressing integral forming technology are avoided, and the problem of a single box body being easily damaged during casting is solved, thereby facilitating industrial applications.

Abstract: The present invention provides a control method of a processor, wherein the control method comprises the steps of: transmitting image data of a first frame to an integrated circuit, wherein the first frame corresponds to a first frame rate; determining a second frame rate of a second frame next to the first frame; determining if a difference between the second frame rate and the first frame rate belongs to a large scale frame rate adjustment or a small scale frame rate adjustment; if the difference between the second frame rate and the first frame rate belongs to the large scale frame rate adjustment, using a first mode to transmit image data of the second frame; and if the difference between the second frame rate and the first frame rate belongs to the small scale frame rate adjustment, using a second mode to transmit image data of the second frame.

Abstract: Semiconductor structures and method of forming the same are provided. A semiconductor structure according to the present disclosure includes a metal feature in a dielectric layer, a passivation structure over the dielectric layer and the metal feature, a contact pad over the passivation structure, and a plurality of contact vias extending through the passivation structure and in contact with the metal feature and the contact pad.

Abstract: The present application provides a soft magnetic alloy sheet, a preparation method therefor and a use thereof. The preparation method comprises the following steps: (1) mixing thermosetting resin, thermoplastic resin, a solvent, a curing agent, and soft magnetic alloy powder having insulating coating to obtain casting slurry; and (2) carrying out degassing and casting-drying treatment on the casting slurry in step (1) in sequence to obtain the soft magnetic alloy sheet.

Abstract: A method and a system for detecting a semiconductor device are provided. The method comprises obtaining an image of the semiconductor device, evaluating a feature of the image, detecting a defect of the semiconductor device based on the feature, extracting a defect information for the defect, calculating a defect die ratio (DDR) in response to the defect and analyzing a relation between the DDR and the defect information.

Abstract: A semiconductor device and method of manufacturing the device that includes a growth die and a dummy die. The method includes patterning, on an integrated circuit wafer, at one least growth die, and patterning at least one dummy die that is positioned on at least a portion of a circumference of the integrated circuit wafer. The patterned growth and dummy dies are etched on the wafer. A bond wave is initiated at a starting point on the integrated circuit wafer. The starting point is positioned on an edge of the integrated circuit wafer opposite the portion on which the at least one dummy die is patterned. Upon application of pressure at the starting point, a uniform bond wave propagates across the wafers, bonding the two wafers together.

Abstract: A semiconductor device and method of manufacturing the device that includes a growth die and a dummy die. The method includes patterning, on an integrated circuit wafer, at one least growth die, and patterning at least one dummy die that is positioned on at least a portion of a circumference of the integrated circuit wafer. The patterned growth and dummy dies are etched on the wafer. A bond wave is initiated at a starting point on the integrated circuit wafer. The starting point is positioned on an edge of the integrated circuit wafer opposite the portion on which the at least one dummy die is patterned. Upon application of pressure at the starting point, a uniform bond wave propagates across the wafers, bonding the two wafers together.

Abstract: A semiconductor device includes a first substrate having opposite first and second sides, a first conductive layer on the first side of the first substrate, and a second substrate having opposite first and second sides. The second side of the second substrate is bonded to the first side of the first substrate. The second substrate includes a semiconductor material, and at least one circuit element electrically coupled to the first conductive layer. The at least one circuit element includes at least one of a Schottky diode configured by the semiconductor material and a first contact structure, a capacitor having a first electrode of the semiconductor material, or a resistor of the semiconductor material.

Abstract: A semiconductor device and method of manufacturing the same that utilizes dielectric pedestals on a sensing electrode. The semiconductor device includes a one or more membranes and an integrated circuit substrate. The integrated circuit substrate includes one or more conductive components disposed within a first dielectric layer on the substrate, with the conductive components interconnected with respective integrated circuit components. The substrate further includes one or more sensing electrodes electrically coupled to the conductive components, and one or more dielectric pedestals positioned within a landing area of the sensing electrode. In addition, the semiconductor device includes at least one cavity that is formed by the membrane positioned over the sensing electrode.

Abstract: Systems, methods, and apparatuses for atomic-scale materials processing based on electron beam induced etching assisted by remote plasma are disclosed. For example, a method may include placing the substrate into a low-pressure chamber to which an electron source is connected. The method may also include contacting the surface of the substrate with reactive particle fluxes produced by a remote plasma source connected to the low-pressure chamber. The remote plasma source may be fed with one or more chemical precursors for surface chemical functionalization of the surface of the substrate. The method may further include electron irradiation of the surface of the substrate with electrons via the electron source at a specified energy level to induce a surface chemical process on the surface of the substrate.

Abstract: A semiconductor device and method of manufacturing the device that includes a growth die and a dummy die. The method includes patterning, on an integrated circuit wafer, at one least growth die, and patterning at least one dummy die that is positioned on at least a portion of a circumference of the integrated circuit wafer. The patterned growth and dummy dies are etched on the wafer. A bond wave is initiated at a starting point on the integrated circuit wafer. The starting point is positioned on an edge of the integrated circuit wafer opposite the portion on which the at least one dummy die is patterned. Upon application of pressure at the starting point, a uniform bond wave propagates across the wafers, bonding the two wafers together.

Abstract: A semiconductor device and method of manufacturing the device that includes a capacitive micromachined ultrasonic transducer (CMUT). The CMUT includes an integrated circuit substrate, and a sensing electrode positioned on the integrated substrate. The sensing electrode includes a sidewall that forms a wall of an isolation trench adjacent to the sensing electrode, and is patterned before covering dielectric layers are deposited. After patterning of the sensing electrode, one or more dielectric layers are patterned, with one dielectric layer patterned on the sensing electrode and sidewall, and which has a thickness corresponding to the surface roughness of the sensing electrode. The CMUT further includes a membrane positioned above the sensing electrode forming a cavity therein.

Abstract: The present invention provides a control method of a processor, wherein the control method comprises the steps of: transmitting image data of a first frame to an integrated circuit, wherein the first frame corresponds to a first frame rate; determining a second frame rate of a second frame next to the first frame; determining if a difference between the second frame rate and the first frame rate belongs to a large scale frame rate adjustment or a small scale frame rate adjustment; if the difference between the second frame rate and the first frame rate belongs to the large scale frame rate adjustment, using a first mode to transmit image data of the second frame; and if the difference between the second frame rate and the first frame rate belongs to the small scale frame rate adjustment, using a second mode to transmit image data of the second frame.

Abstract: The present invention provides a control method of a processor, wherein the control method comprises the steps of: transmitting image data of a first frame to an integrated circuit, wherein the first frame corresponds to a first frame rate; determining a second frame rate of a second frame next to the first frame; determining if a difference between the second frame rate and the first frame rate belongs to a large scale frame rate adjustment or a small scale frame rate adjustment; if the difference between the second frame rate and the first frame rate belongs to the large scale frame rate adjustment, using a first mode to transmit image data of the second frame; and if the difference between the second frame rate and the first frame rate belongs to the small scale frame rate adjustment, using a second mode to transmit image data of the second frame.

Abstract: Provided is a method of selectively etching a substrate comprising at least one cycle of: depositing a chemical precursor on a surface of the substrate to form a chemical precursor layer on the substrate, the substrate comprising a first portion and a second portion, wherein the first and the second portion are of a different composition; selectively removing the chemical precursor layer and at least a part of the first portion of the substrate; and repeating the cycle until the first portion of the substrate is substantially or completely removed, wherein deposition of the chemical precursor and selective removal of the chemical precursor layer and at least a part of the first portion of the substrate are performed under a plasma environment.