Patents by Inventor Kang-young Cho

Kang-young Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240134478
    Abstract: A method of driving an electronic device includes displaying a plurality of fingerprint recognition icons on a display device configured to perform fingerprint recognition, and releasing a lock state of the display device through a fingerprint authentication process upon determining at least one first fingerprint recognition icon among the plurality of fingerprint recognition icons is touched. The plurality of fingerprint recognition icons include at least one first fingerprint recognition icon configured to support the fingerprint recognition and at least one second fingerprint recognition icon configured to not support the fingerprint recognition.
    Type: Application
    Filed: September 7, 2023
    Publication date: April 25, 2024
    Inventors: Byung Han YOO, Jung Woo PARK, Hyang A PARK, Dae Young LEE, Hyun Dae LEE, Kang Bin JO, Sang Hwan CHO, Sung-Chan JO
  • Publication number: 20170036958
    Abstract: Disclosed are: an environment-friendly artificial marble which can release a coffee scent and shows a pleasing natural aesthetic by adding ground brewed coffee or coffee by-products, which are the grounds discarded when coffee is made with coffee powder or brewed coffee and the like, during the manufacture of an artificial marble; and a method for manufacturing the same.
    Type: Application
    Filed: April 17, 2014
    Publication date: February 9, 2017
    Inventors: Kang Young Cho, Guk Tae Kim, Sang Hyun Lee, Jin Su Yeo, Ju Do Eom
  • Patent number: 8675432
    Abstract: Provided is a semiconductor device capable of effectively testing whether memory cells and a memory cell array are defective. The semiconductor device may include a memory cell array having a plurality of memory cells and an external test pad connected to an internal test pad. A test voltage may be applied to the plurality of word lines connected to the plurality of memory cells via the external test pad and the internal test pad in a test mode, wherein the test voltage disables the plurality of word lines.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: March 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hee-Il Hong, Kang-Young Cho
  • Publication number: 20120187977
    Abstract: Provided is a semiconductor device capable of effectively testing whether memory cells and a memory cell array are defective. The semiconductor device may include a memory cell array having a plurality of memory cells and an external test pad connected to an internal test pad. A test voltage may be applied to the plurality of word lines connected to the plurality of memory cells via the external test pad and the internal test pad in a test mode, wherein the test voltage disables the plurality of word lines.
    Type: Application
    Filed: April 2, 2012
    Publication date: July 26, 2012
    Inventors: Hee-Il Hong, Kang-Young Cho
  • Patent number: 8149637
    Abstract: Provided is a semiconductor device capable of effectively testing whether memory cells and a memory cell array are defective. The semiconductor device may include a memory cell array having a plurality of memory cells and an external test pad connected to an internal test pad. A test voltage may be applied to the plurality of word lines connected to the plurality of memory cells via the external test pad and the internal test pad in a test mode, wherein the test voltage disables the plurality of word lines.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: April 3, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hee-Il Hong, Kang-Young Cho
  • Publication number: 20100296353
    Abstract: Provided is a semiconductor device capable of effectively testing whether memory cells and a memory cell array are defective. The semiconductor device may include a memory cell array having a plurality of memory cells and an external test pad connected to an internal test pad. A test voltage may be applied to the plurality of word lines connected to the plurality of memory cells via the external test pad and the internal test pad in a test mode, wherein the test voltage disables the plurality of word lines.
    Type: Application
    Filed: February 2, 2010
    Publication date: November 25, 2010
    Inventors: Hee-Il Hong, Kang-Young Cho
  • Patent number: 7460428
    Abstract: Provided is a DRAM having reduced current consumption and a communication terminal including the same. The DRAM includes a plurality of memory banks capable of being independently supplied with power, and a DPD controller for selectively causing some of the plurality of memory banks to enter a DPD mode.
    Type: Grant
    Filed: July 7, 2006
    Date of Patent: December 2, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-hoon Joo, Sang-seok Kang, Byung-heon Kwak, Kang-young Cho, Chang-hag Oh
  • Publication number: 20070008802
    Abstract: Provided is a DRAM having reduced current consumption and a communication terminal including the same. The DRAM includes a plurality of memory banks capable of being independently supplied with power, and a DPD controller for selectively causing some of the plurality of memory banks to enter a DPD mode.
    Type: Application
    Filed: July 7, 2006
    Publication date: January 11, 2007
    Inventors: Jae-hoon Joo, Sang-seok Kang, Byung-heon Kwak, Kang-young Cho, Chang-hag Oh