Abstract: A semiconductor integrated circuit design method and apparatus, and relates to the technical field of semiconductors are provided. The semiconductor integrated circuit design method includes: determining, based on an original layout, an original length of an end of a gate structure extending out of an active region in which the gate structure is located; redetermining, based on a preset rule and the original length, a correction length of the end of the gate structure extending out of the active region in which the gate structure is located; and integrating the original layout and the correction lengths, and forming an updated layout.

Abstract: A method for checking a Design for Test (DFT) circuit includes: transmitting a control signal to the DFT circuit to determine test mode signals output by the DFT circuit, with the DFT circuit being configured to sequentially select multiple address latches according to the control signal to output the test mode signals; analyzing the test mode signals to determine whether the multiple address latches in the DFT circuit have an error; and outputting a simulation result report.

Abstract: A full-automatic cat toilet is provided, which includes: a base; an accommodating cavity arranged in the base for placing cat litter; and a rotating shovel; wherein the rotating shovel has two ends rotatably arranged on the base, and a rotating shovel claw arranged at a radial end thereof; the rotating shovel and the rotating shovel claw are capable of rotating so as to unload the cat litter into the accommodating cavity, the accommodating cavity is located below the rotating shovel and the rotating shovel claw.

Abstract: A layout method for an integrated circuit includes the following steps: providing a layout, the layout including a first element region and a second element region, a spacing region being provided between the first element region and the second element region; and detecting whether a width of the spacing region is less than a preset width, and if yes, marking at least one of the first element region, the second element region and the spacing region, the preset width being a minimum width meeting a requirement, wherein the requirement is to fill the spacing region with at least one dummy pattern. A layout apparatus employing the layout method for the integrated circuit can quickly and accurately position a poorly-placed element region in the layout, improve the layout efficiency and layout precision of the integrated circuit, and lay a foundation for improving photolithography quality.

Abstract: The present disclosure provides a method and a system for quickly determining transient stability of a half-wavelength transmission system. The method includes: obtaining power and a power angle of a feeding-end generator of a half-wavelength transmission system; and determining transient power angle stability and a power angle instability mode of the half-wavelength transmission system by using a constructed index system, where two power angle instability modes, that is, an instability mode 1 and an instability mode 2, are specifically constructed for the half-wavelength transmission system based on an equal area method. Based on the equal area method, the present disclosure constructs two instability modes specific to the half-wavelength transmission system, so as to accurately describe transient power angle characteristics of the half-wavelength transmission system under a severe fault, and characteristics of the two instability modes are significantly different from those of an AC transmission mode.

Abstract: A method for obtaining circuit noise parameters and an electronic device are provided. The method includes: determining a plurality of circuits to be tested, where each circuit includes one or more signal lines, and each circuit has at least one operating state; obtaining a parasitic capacitance between each signal line and all others signal lines, and determining a logic state of each signal line under each of the operating states; determining a plurality of operating state combinations for the plurality of circuits to be tested, and determining one target operating state combination from the plurality of operating state combinations; and under the target operating state combination, determining noise parameters of each one of the signal lines to be tested according to the logic state of each one of the signal lines to be tested and the parasitic capacitance.

Abstract: The present disclosure provides a method and a system for quickly determining transient stability of a half-wavelength transmission system. The method includes: obtaining power and a power angle of a feeding-end generator of a half-wavelength transmission system; and determining transient power angle stability and a power angle instability mode of the half-wavelength transmission system by using a constructed index system, where two power angle instability modes, that is, an instability mode 1 and an instability mode 2, are specifically constructed for the half-wavelength transmission system based on an equal area method. Based on the equal area method, the present disclosure constructs two instability modes specific to the half-wavelength transmission system, so as to accurately describe transient power angle characteristics of the half-wavelength transmission system under a severe fault, and characteristics of the two instability modes are significantly different from those of an AC transmission mode.

Abstract: Embodiments of the present application provide a method and an apparatus for adjusting metal wiring density. By detecting metal wiring density in each of metal density detection windows in a target layout, a region in which the metal wiring density is greater than a preset density threshold can be quickly positioned in the target layout, thereby improving the layout correction efficiency; then a power fill mesh in a target metal density detection window in which the metal wiring density is greater than the preset density threshold is cropped multiple times, until the metal wiring density in each of the metal density detection windows is less than or equal to the preset density threshold, such that sufficient power fill meshes are retained in the target layout while the metal wiring density of the target layout is less than or equal to the preset density threshold.

Abstract: Embodiments of the application disclose a check tool and a check method for a Design Rule Check (DRC) rule deck of an integrated circuit layout. The check tool (100) for the DRC rule deck of the integrated circuit layout includes: an intelligent database creation engine (110), configured to generate a test case database; an intelligent arrangement engine (120), configured to generate a standard integrated circuit layout (150) according to the test case database; and an intelligent detection and analysis engine (130), configured to detect and analyze a target DRC rule deck (140) of the integrated circuit layout according to the standard integrated circuit layout (150).

Abstract: A flexible display module, a manufacturing method thereof, and a flexible display device are provided. The flexible display module includes a flexible display panel; a back plate, a buffer material layer, a first adhesive layer, and a metal plate under the flexible display panel; a polarizer, a second adhesive layer, and a cover plate on the flexible display panel. The back plate is positioned in a non-bending area. The buffer material layer is positioned in a bending area and is disposed in a same layer as the back plate. A side of the first adhesive layer is bonded to the back plate and the buffer material layer, and another side thereof is bonded to the metal plate.

Abstract: The present application relates to a circuit simulation test method and apparatus, a device, and a medium. The method includes: creating a parametric data model, wherein the parametric data model is configured to generate preset write data based on a preset parameter; creating a test platform, wherein the test platform is configured to generate a test result based on the preset write data; creating an eye diagram generation module, wherein the eye diagram generation module is configured to generate a data eye diagram based on the test result; and conducting a simulation test, inputting the preset write data to the test platform and obtaining the test result, and generating the data eye diagram by using the eye diagram generation module.

Abstract: A method for checking a Design for Test (DFT) circuit includes: transmitting a control signal to the DFT circuit to determine test mode signals output by the DFT circuit, with the DFT circuit being configured to sequentially select multiple address latches according to the control signal to output the test mode signals; analyzing the test mode signals to determine whether the multiple address latches in the DFT circuit have an error; and outputting a simulation result report.

Abstract: Embodiments of the present disclosure relate to the field of semiconductor circuit design and provide an analysis system for signal eye diagrams and method. The analysis system includes: a display structure, configured to receive a plurality of pieces of first display information of a plurality of groups of signal eye diagrams, receive second display information of a standard effective region generated based on an industry standard, display all the signal eye diagrams based on the first display information, and display an outer edge of the standard effective region based on the second display information, where each signal eye diagram corresponds to one piece of first display information, different signal eye diagrams are located in different layers, and different signal eye diagrams are displayed in different ways.