Abstract: The present disclosure discloses a method of generating a master state that is a normal state in a repeated cycle by analyzing log data output from a programmable logic controller (PLC). In addition, a method of generating log data as graph data as data preprocessing for generating a master state is disclosed. The method of generating a master pattern and the method of training a cycle analysis model according to the present disclosure are different from the related art in that the methods are a technology of processing a machine control language (low-level language) that is difficult for humans to analyze and converting the machine control language into an analyzable language (high-level language), i.e., a machine language processing (MLP)-based technology that analyzes the executed machine language (a language that controls a machine) with a computer and can be understood by humans.

Abstract: In an embodiment of the present invention, a method for displaying an image of a display device includes moving the image displayed on an image display region along a movement path including a first position and a second position during a period of time, wherein, during the period of time, a total time for which the image is located at the first position is greater than a total time for which the image is located at the second position.

Abstract: A method of displaying an image in a display device may include determining the degree of deterioration of pixels included in a display unit based on image data of a current frame image, determining a shift route of the current frame image so as to correspond to the determined degree of deterioration. The first image data is corrected to second image data so that the current frame image is shifted along the shift route.

Abstract: A display includes: a display panel; and a panel bottom sheet disposed below the display panel, the panel bottom sheet including: a first heat dissipation layer; a second heat dissipation layer over the first heat dissipation layer, including a first opening formed completely through the second heat dissipation layer in a thickness direction; a heat dissipation coupling interlayer between the first heat dissipation layer and the second heat dissipation layer, and a heat dissipation substrate on the second heat dissipation layer.

Abstract: A device for controlling a user interface may include a sensor configured to acquire information associated with a passenger of a vehicle, a user interface device configured to receive at least one user input of the passenger, and a processor. The processor may monitor, based on the information associated with the passenger, the passenger, determine, based on an abnormality associated with an appearance of the passenger, a passenger type for the passenger, and provide, based on the passenger type for passenger and via the user interface device, a user interface associated with the passenger type, wherein the user interface associated with the passenger type is configured to reduce a task completion time for the passenger type.

Abstract: A display device including a controller and a display panel. The controller receives original image data and output a display image signal. The display panel receives the display image signal and displays a display image corresponding to the display image signal. The controller includes an image shift controller and a memory. The image shift controller generates shifted image data by modulating the original image data to shift the display image sequentially along a preset shift path on the display panel. The memory stores a shift path value indicating a distance by which the display image has been shifted on the preset shift path. The image shift controller generates the display image signal by processing the shifted image data. When the display device is powered on, the image shift controller generates shifted image data corresponding to a shift path value stored in the memory.

Abstract: A motor drive device includes: a first inverter including a plurality of first switching elements and connected to a plurality of coils; a second inverter including a plurality of second switching elements and connected to the plurality of coils; a plurality of transfer switching elements connected to the second ends; a capacitor disposed at one side of a casing of a motor; first and second cooling channels disposed at both sides of the capacitor; a plurality of first power modules including some of the plurality of first switching elements and some of the transfer switching elements; and a plurality of second power modules including some of the plurality of second switching elements.

Abstract: In an embodiment of the present invention, a method for displaying an image of a display device includes moving the image displayed on an image display region along a movement path including a first position and a second position during a period of time, wherein, during the period of time, a total time for which the image is located at the first position is greater than a total time for which the image is located at the second position.

Abstract: The present disclosure relates to an apparatus for recognizing a pulse signal, and more particularly, to an apparatus for recognizing a pulse signal, which maintains the pulse signal being input for a scan time until an end time point of the scan time, and stores the pulse signal in a pulse signal storage area as pulse input data. The apparatus for recognizing a pulse signal according to one embodiment of the present disclosure includes a signal maintaining unit configured to maintain and output the pulse signal, which is input for the scan time, as a pulse maintaining signal; a signal transmission unit configured to receive the pulse maintaining signal from the signal maintaining unit and transmit the input pulse maintaining signal; and a control unit configured to output the transmission control signal to the signal transmission unit to receive and store the received pulse maintaining signal.

Abstract: Disclosed embodiments include a method of using a general-purpose microprocessor to debug a programmable logic controller. In some embodiments, the method includes: at a MPU of the PLC, backing up identification information and file information of an interrupt step of steps comprised in a user's program and substituting the interrupt step with an exceptional interrupt code to set the interrupt step for the debugging; and at the MPU of the PLC, interrupting the driving of the PLC at a step including the exceptional interrupt code in executing the user's program step by step while driving the PLC.

Abstract: The present disclosure relates to an apparatus for recognizing a pulse signal, and more particularly, to an apparatus for recognizing a pulse signal, which maintains the pulse signal being input for a scan time until an end time point of the scan time, and stores the pulse signal in a pulse signal storage area as pulse input data. The apparatus for recognizing a pulse signal according to one embodiment of the present disclosure includes a signal maintaining unit configured to maintain and output the pulse signal, which is input for the scan time, as a pulse maintaining signal; a signal transmission unit configured to receive the pulse maintaining signal from the signal maintaining unit and transmit the input pulse maintaining signal; and a control unit configured to output the transmission control signal to the signal transmission unit to receive and store the received pulse maintaining signal.

Abstract: Disclosed herein are a PLC high speed counter and an operating method thereof. The PLC high speed counter includes: an input circuit configured to convert and output a high-speed pulse train input from an encoder into a CMOS level; a micro processor unit configured to receive the pulse train from the input circuit, generate a count value by counting the pulse train in a linear count manner and calculate a current ring count value based on the count value; and a buffer configured to receive the count value from the micro processor unit and store the same as a current linear count value, wherein, when a current value request is received from an external device, the micro processor unit determines an operation mode and transmits, if the operation mode is a ring counter mode, the current ring count value.

Abstract: Disclosed embodiments include a method of using a general-purpose microprocessor to debug a programmable logic controller. In some embodiments, the method includes: at a MPU of the PLC, backing up identification information and file information of an interrupt step of steps comprised in a user's program and substituting the interrupt step with an exceptional interrupt code to set the interrupt step for the debugging; and at the MPU of the PLC, interrupting the driving of the PLC at a step including the exceptional interrupt code in executing the user's program step by step while driving the PLC.

Abstract: The present disclosure relates to an apparatus for simplification of input signal configured to simplify a process of microprocessor and to enhance a speed by transforming six input modes of 1-phase/2-input/1-multiplication mode, 1-phase/2-input/2-multiplication mode, CW/CCW mode, 2-phase/1-multiplication mode, 2-phase/2-multiplication mode and 2-phase/4-multiplication mode to a same shape according to types of encoder connected to a PLC high speed counter, and transmitting to the microprocessor, and by adding the six types of input modes to a logic gate circuit of a high speed counter input circuit.

Abstract: Disclosed herein are a PLC high speed counter and an operating method thereof. The PLC high speed counter includes: an input circuit configured to convert and output a high-speed pulse train input from an encoder into a CMOS level; a micro processor unit configured to receive the pulse train from the input circuit, generate a count value by counting the pulse train in a linear count manner and calculate a current ring count value based on the count value; and a buffer configured to receive the count value from the micro processor unit and store the same as a current linear count value, wherein, when a current value request is received from an external device, the micro processor unit determines an operation mode and transmits, if the operation mode is a ring counter mode, the current ring count value.

Abstract: Disclosed is a apparatus and method for detecting a cut-off frequency of a pulse signal, the apparatus including an input processor configured to generate a second pulse signal at a time when a rising edge and a falling edge of a first pulse signal appear, in a case the first pulse signal, which is a pulse signal of a monitoring object, is inputted, a counter configured to count a clock signal relative to the second pulse signal generated by the input processor, a reset processor configured to reset the counter at every predetermined (set) period, and a detector configured to generate and output a cut-off frequency of a detection signal, in a case an output value of the counter exceeds a predetermined (set) threshold during the predetermined period.

Abstract: The present disclosure relates to an apparatus for simplification of input signal configured to simplify a process of microprocessor and to enhance a speed by transforming six input modes of 1-phase/2-input/1-multiplication mode, 1-phase/2-input/2-multiplication mode, CW/CCW mode, 2-phase/1-multiplication mode, 2-phase/2-multiplication mode and 2-phase/4-multiplication mode to a same shape according to types of encoder connected to a PLC high speed counter, and transmitting to the microprocessor, and by adding the six types of input modes to a logic gate circuit of a high speed counter input circuit.

Abstract: Disclosed is a apparatus and method for detecting a cut-off frequency of a pulse signal, the apparatus including an input processor configured to generate a second pulse signal at a time when a rising edge and a falling edge of a first pulse signal appear, in a case the first pulse signal, which is a pulse signal of a monitoring object, is inputted, a counter configured to count a clock signal relative to the second pulse signal generated by the input processor, a reset processor configured to reset the counter at every predetermined (set) period, and a detector configured to generate and output a cut-off frequency of a detection signal, in a case an output value of the counter exceeds a predetermined (set) threshold during the predetermined period.