Abstract: Disclosed herein is a method for memory management in a memory disaggregation environment. The method includes generating virtual memory based on multiple first memory devices, determining whether a condition for allocation acceleration is satisfied by the first memory devices, and allocating a memory page to the first memory devices based on whether the condition for allocation acceleration is satisfied.

Abstract: The present disclosure relates to semiconductor memory devices. An example semiconductor memory device includes a cell region and a peripheral circuit region electrically connected with the cell region. The cell region includes a plurality of gate electrodes spaced apart from each other and stacked in a vertical direction, and a channel structure extending through the plurality of gate electrodes in the vertical direction. The peripheral circuit region includes a substrate, a first element isolation structure, a first gate structure on the first active region, a second element isolation structure, a second gate structure on the second active region, a third element isolation structure, and a third gate structure on the third active region. The third element isolation structure includes a first element isolation pattern and a second element isolation pattern. The first element isolation pattern and the second element isolation pattern include different materials from each other.

Abstract: Provided is a power management device including a first power domain operating in a sleep mode consuming minimal power, and a second power domain turned on exclusively when a wake signal is received from an external device within a communication range of the first power domain, wherein the first power domain includes an always-on Digital Low-DropOut (DLDO), and the second power domain includes a main Low-DropOut (LDO), and split sequence control is performed on power management in the first power domain and the second power domain.

Abstract: A technology related to a transmission device of an amplitude modulation method is disclosed. In the amplitude modulation transmission device, a transmission data signal transformed into a sinusoidal wave transition form is input to a signal input stage of a cascode power amplifier, and a transmission data signal transformed into another sinusoidal wave transition form is input to a bias power stage of the cascode power amplifier. The transmission data signal transformed into the sinusoidal wave transition form has a sinusoidal wave form in a section in which input data transitions and maintain its previous value in a section in which the input data is maintained.

Abstract: An electronic device includes a housing, a slot disposed in an interior of the housing, wherein the slot is configured to permit an electronic module inserted into the slot, a cooling member disposed outside the slot to cool the electronic module, and a heat transfer member configured to be connected to the electronic module to transfer heat from the electronic module to the cooling member.

Abstract: A core body temperature measurement device includes a body and an operation unit. The body is fixed to an ear canal of user. The operation unit is combined with a front side of the body, and is configured to be exposed to the ear canal or to be concealed inside, and has a sensor part. the sensor part measures a core body temperature of user when the operation unit is exposed to the ear canal.

Abstract: Disclosed herein is a method for memory management in a memory disaggregation environment. The method includes generating virtual memory based on multiple first memory devices, determining whether a condition for allocation acceleration is satisfied by the first memory devices, and allocating a memory page to the first memory devices based on whether the condition for allocation acceleration is satisfied.

Abstract: A semiconductor memory device comprises a cell structure and a peripheral circuit structure electrically connected to the cell structure. The peripheral circuit structure comprises an active region, a first gate structure comprising a first gate insulating layer intersecting the active region and in contact with the active region, a second gate structure comprising a second gate insulating layer spaced apart from the first gate structure, and in contact with the active region, and a source/drain region between the first gate structure and the second gate structure. A thickness of the first gate insulating layer is less than a thickness of the second gate insulating layer. The source/drain region comprises a first region adjacent to the first gate structure and a second region adjacent to the second gate structure. A depth of the first region is equal to a depth of the second region.

Abstract: The embodiments relate to a polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors, to a process for preparing the same, and to a process for preparing a semiconductor device using the same. The polishing pad according to the embodiment adjusts the surface roughness characteristics of the polishing pad after polishing, whereby the polishing rate can be enhanced, and the surface residues, surface scratches, and chatter marks of the wafer can be remarkably reduced.

Abstract: A correlation tolerance limit setting system using repetitive cross-validation includes: a variable extraction unit randomly classifying data of an initial DB set into training set data and validation set data at a specific rate and then extracting variables for determining a DNBR limit by optimizing coefficients of a selected correlation; a normality test unit testing normality for a variable extraction result; a DNBR limit unit determining whether data sets have a same population or not depending on normality result and determining DNBR limit from a distribution of 95/95 DNBR; and a controller.

Abstract: A correlation tolerance limit setting system using repetitive cross-validation includes: a variable extraction unit randomly classifying data of an initial DB set into training set data and validation set data at a specific rate and then extracting variables for determining a DNBR limit by optimizing coefficients of a selected correlation; a normality test unit testing normality for a variable extraction result; a DNBR limit unit determining whether data sets have a same population or not depending on normality result and determining DNBR limit from a distribution of 95/95 DNBR; and a controller.

Abstract: A system and method are provided for setting a tolerance limit of a correlation by using repetitive cross-validation to prevent intentional or unintentional distortion of data characteristics by human intervention or otherwise, and to prevent risk caused thereby, and to quantify the influence of the distortion of the data characteristics in fitting the correlation and setting the tolerance limit. The system for setting the tolerance limit of the correlation by using repetitive cross-validation according to an embodiment of this presentation includes a variable extraction unit extracting a variable by partitioning a training set and a validation set and by fitting the correlation coefficients; a normality test unit performing a normality test for variable extraction results; and a DNBR limit unit performing a same population test, and determining an allowable DNBR limit for a DNBR value distribution, based upon normality.

Abstract: Disclosed is a spacer grid assembly with mixing vanes supporting fuel rods of nuclear fuel assemblies and mixing coolant that flows around the fuel rods, and more particularly, a spacer grid equipped with mixing vanes that mix coolant flowing around fuel rods. The spacer grid with hydraulically balanced mixing vane patterns, in the spacer grid equipped with a strip dividing a plurality of unit grid cells and a plurality of springs, protruded in uniform directions of vertical and horizontal directions on a grid surface of the strip and supporting nuclear fuel rods, which includes: a plurality of mixing vanes protruded to the downstream of coolant on an upper end of the inner grid surface, wherein positions and directions of the mixing vanes are formed in regular patterns on the spacer grid. Thus, it can minimize coolant flow induced vibration of the spacer grid by balancing hydraulic load generated by the mixing vanes, around the center of the spacer grids.