Abstract: An image sensor is disclosed. The image sensor includes a semiconductor substrate, a plurality of pillars protruding from the semiconductor substrate, and spaced from each other, a spacer layer on the semiconductor substrate and a sidewall of each of the plurality of pillars, a plurality of gate structures on the spacer layer, and a plurality of unit pixels arranged in a matrix form. The first unit pixel includes a first photodiode (PD) formed in the semiconductor substrate, a first pillar, a second pillar and a third pillar of the plurality of pillars, and a first gate structure and a second gate structure of the plurality of gate structures. Each of the first pillar and the second pillar includes a first channel region and a first drain region on the first channel region. The third pillar is not surround by any gate structure of the plurality of gate structures.

Abstract: An image sensor includes a plurality of unit pixels, each including: a substrate including first and second sides which are opposite to each other, a photoelectric conversion layer in the substrate, and a wiring structure on the first side of the substrate. The wiring structure may include: a first capacitor, a second capacitor spaced from the first capacitor, a plurality of edge vias arranged along edges of the unit pixel, and a plurality of central vias interposed between the first capacitor and the second capacitor.

Abstract: An image sensor includes a plurality of unit pixels, each including: a substrate including first and second sides which are opposite to each other, a photoelectric conversion layer in the substrate, and a wiring structure on the first side of the substrate. The wiring structure may include: a first capacitor, a second capacitor spaced from the first capacitor, a plurality of edge vias arranged along edges of the unit pixel, and a plurality of central vias interposed between the first capacitor and the second capacitor.

Abstract: Image sensors may include a semiconductor substrate including a first surface and a second surface opposite the first surface and including a plurality of pixels, a first pixel isolation structure including a first trench recessed from the first surface of the semiconductor substrate into the semiconductor substrate and a conductive layer in the first trench, and a second pixel isolation structure including a second trench and a third trench each recessed from the second surface of the semiconductor substrate into the semiconductor substrate and a dielectric layer in the second trench and the third trench. The first pixel isolation structure and the second pixel isolation structure may contact each other and separate the pixels from each other in the semiconductor substrate.

Abstract: An image sensor may include a first substrate having first and second surfaces and including unit pixel regions, each of which includes a device isolation pattern and a photoelectric conversion region adjacent to the first surface of the first substrate, a pixel isolation pattern provided in the first substrate to define the unit pixel regions and to penetrate the device isolation pattern, a first impurity region and a floating diffusion region provided in the first substrate and adjacent to the first surface, a second substrate provided on the first substrate to have third and fourth surfaces, a second impurity region provided in the second substrate and adjacent to the third surface, and ground and body contacts coupled to the first and second impurity regions, respectively. The ground contact and the body contact may be electrically separated from each other.

Abstract: An image sensor includes a plurality of unit pixels, each including: a substrate including first and second sides which are opposite to each other, a photoelectric conversion layer in the substrate, and a wiring structure on the first side of the substrate. The wiring structure may include: a first capacitor, a second capacitor spaced from the first capacitor, a plurality of edge vias arranged along edges of the unit pixel, and a plurality of central vias interposed between the first capacitor and the second capacitor.

Abstract: A semiconductor device is provided including an active region on a substrate A plurality of channel layers is spaced apart on the active region. Gate structures are provided. The gate structures intersect the active region and the plurality of channel layers. The gate structures surround the plurality of channel layers. Source/drain regions are disposed on the active region on at least one side of the gate structures. The source/drain regions contact with the plurality of channel layers. A lower insulating layer is disposed between side surfaces of the gate structures on the source/drain regions. Contact plugs penetrate through the lower insulating layer. The contact plugs contact the source/drain regions. An isolation structure intersects the active region on the substrate and is disposed between the source/drain regions adjacent to each other. Each of the gate structures includes a gate electrode and a gate capping layer including materials different from each other.

Abstract: An image sensor includes a substrate which includes a plurality of unit pixels. Each of the plurality of unit pixels includes a photoelectric conversion layer. A pixel separation pattern is disposed in the substrate and has a and shape that includes a plurality of grid points. The pixel separation pattern is configured to separate each of the plurality of unit pixels from each other. A support structure is disposed in the substrate and is positioned to correspond to the plurality of grid points of the pixel separation pattern. The support structure is configured to support adjacent unit pixels of the plurality of unit pixels.

Abstract: An image sensor is disclosed. The image sensor includes first, second, third and fourth unit pixels. Each of the unit pixels includes a first transfer transistor structure, a second transfer transistor structure and a third transfer transistor structure, a first source follower transistor structure, a second source follower transistor structure and a third source follower transistor structure, and a first selection transistor structure, a second selection transistor structure and a third selection transistor structure, the fourth unit pixel includes a fourth transfer transistor structure and a reset transistor structure, and each of the transfer transistor structures includes a channel electrode and a gate structure that surrounds side surfaces of the channel electrode.

Abstract: A semiconductor device is provided including an active region on a substrate A plurality of channel layers is spaced apart on the active region. Gate structures are provided. The gate structures intersect the active region and the plurality of channel layers. The gate structures surround the plurality of channel layers. Source/drain regions are disposed on the active region on at least one side of the gate structures. The source/drain regions contact with the plurality of channel layers. A lower insulating layer is disposed between side surfaces of the gate structures on the source/drain regions. Contact plugs penetrate through the lower insulating layer. The contact plugs contact the source/drain regions. An isolation structure intersects the active region on the substrate and is disposed between the source/drain regions adjacent to each other. Each of the gate structures includes a gate electrode and a gate capping layer including materials different from each other.

Abstract: A semiconductor device includes a substrate, an active region disposed on the substrate and extending in a first direction, a device isolation layer adjacent to the active region, a gate structure disposed in the active region, the gate structure extending in a second direction crossing the first direction, and covering a portion of the device isolation layer, a gate separation pattern contacting an end of the gate structure, and an impurity region disposed below the gate separation pattern and on the device isolation layer.

Abstract: A semiconductor device includes a substrate, an active region disposed on the substrate and extending in a first direction, a device isolation layer adjacent to the active region, a gate structure disposed in the active region, the gate structure extending in a second direction crossing the first direction, and covering a portion of the device isolation layer, a gate separation pattern contacting an end of the gate structure, and an impurity region disposed below the gate separation pattern and on the device isolation layer.