Patents by Inventor Kangping Zhang

Kangping Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240141070
    Abstract: Provided is an isolated antigen-binding protein, wherein the drug is used for the treatment of tumor, and the isolated antigen-binding protein comprises a PD-L1 binding moiety and an OX40 binding moiety, wherein: the OX40 binding moiety is capable of recognizing and/or binding amino acid residues G70 and/or F71 in a human OX40 extracellular domain; and the PD-L1 binding moiety is capable of recognizing and/or binding amino acid residues I54, Y56, E58, Q66 and/or R113 in an N-terminal IgV domain of human PD-L1. Further provided is a use of the isolated antigen-binding protein in preparing a drug, wherein the drug is used for the treatment of tumors.
    Type: Application
    Filed: October 16, 2020
    Publication date: May 2, 2024
    Inventors: Ting XU, Pilin WANG, Kangping GUO, Yuhao JIN, Ting CHEN, Li GAO, Qingqing ZHANG
  • Patent number: 7851273
    Abstract: In the present invention, a method of testing an unpackaged integrated circuit die is disclosed. The die has a plurality of first input/output pads. A serial electrical connection is fabricated in the die between all of the input/output pads of the die which are not of the first plurality (hereinafter: “second plurality”). The second plurality has a start input and an end output. The start input of the second plurality is connected to the output of one selected input buffer of the input pad of the first plurality and the end output of the second plurality is also connected to the input of one selected output pad of the first plurality. The second plurality of input/output pads are tested through selected input pad and selected output pad of the first plurality without electrical probes making contact during the wafer sort. The present invention also relates to an integrated circuit die so fabricated as to facilitate testing.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: December 14, 2010
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Kangping Zhang, Fong Long Lin
  • Publication number: 20100203654
    Abstract: In the present invention, a method of testing an unpackaged integrated circuit die is disclosed. The die has a plurality of first input/output pads. A serial electrical connection is fabricated in the die between all of the input/output pads of the die which are not of the first plurality (hereinafter: “second plurality”). The second plurality has a start input and an end output. The start input of the second plurality is connected to the output of one selected input buffer of the input pad of the first plurality and the end output of the second plurality is also connected to the input of one selected output pad of the first plurality. The second plurality of input/output pads are tested through selected input pad and selected output pad of the first plurality without electrical probes making contact during the wafer sort. The present invention also relates to an integrated circuit die so fabricated as to facilitate testing.
    Type: Application
    Filed: April 19, 2010
    Publication date: August 12, 2010
    Applicant: Silicon Storage Technology, Inc.
    Inventors: Kangping Zhang, Fong-Long Lin
  • Patent number: 7728361
    Abstract: In the present invention, a method of testing an unpackaged integrated circuit die is disclosed. The die has a plurality of first input/output pads. A serial electrical connection is fabricated in the die between all of the input/output pads of the die which are not of the first plurality (hereinafter: “second plurality”). The second plurality has a start input and an end output. The start input of the second plurality is connected to the output of one selected input buffer of the input pad of the first plurality and the end output of the second plurality is also connected to the input of one selected output pad of the first plurality. The second plurality of input/output pads are tested through selected input pad and selected output pad of the first plurality without electrical probes making contact during the wafer sort. The present invention also relates to an integrated circuit die so fabricated as to facilitate testing.
    Type: Grant
    Filed: May 1, 2008
    Date of Patent: June 1, 2010
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Kangping Zhang, Fong-Long Lin
  • Publication number: 20090273007
    Abstract: In the present invention, a method of testing an unpackaged integrated circuit die is disclosed. The die has a plurality of first input/output pads. A serial electrical connection is fabricated in the die between all of the input/output pads of the die which are not of the first plurality (hereinafter: “second plurality”). The second plurality has a start input and an end output. The start input of the second plurality is connected to the output of one selected input buffer of the input pad of the first plurality and the end output of the second plurality is also connected to the input of one selected output pad of the first plurality. The second plurality of input/output pads are tested through selected input pad and selected output pad of the first plurality without electrical probes making contact during the wafer sort. The present invention also relates to an integrated circuit die so fabricated as to facilitate testing.
    Type: Application
    Filed: May 1, 2008
    Publication date: November 5, 2009
    Inventors: Kangping Zhang, Fong-Long Lin