Abstract: In a 3D semiconductor memory device, a stack structure includes electrodes and first insulating layers disposed between the electrodes. The stack structure has a stair structure on a connection region. A vertical channel structure penetrates the stack structure on a cell array region. A vertical dummy structure penates the stair structure on the connection region. A second insulating layer is selectively disposed on the cell array region. A maximum thickness of the second insulating layer ranges from 1.5 times to 10 times a maximum thickness of the first insulating layer on the second insulating layer. The vertical channel structure includes an abrupt diameter change at a level of a top surface of the second insulating layer. The abrupt diameter change has a surface which is parallel to the top surface of the second insulating layer and is substantially coplanar with the top surface of the second insulating layer.

Abstract: A three-dimensional semiconductor memory device includes; a first block and a second block arranged on a first substrate in a first direction, wherein each of the first block and the second block includes electrode layers stacked on the first substrate, a source layer interposed between the first block and the first substrate, and between the second block and the first substrate, a first insulating separation pattern interposed between the first block and the second block and extending in the first direction, wherein the first insulating separation pattern includes a line portion and a protruding portion, the line portion extending in a second direction crossing the first direction, and the protruding portion having a width greater than a width of the line portion, a first source contact plug penetrating the protruding portion of the first insulating separation pattern to electrically connect the source layer, and at least one through via penetrating the source layer and at least one of the first block and th

Abstract: In a 3D semiconductor memory device, a stack structure includes electrodes and first insulating layers disposed between the electrodes. The stack structure has a stair structure on a connection region. A vertical channel structure penetrates the stack structure on a cell array region. A vertical dummy structure penetrates the stair structure on the connection region. A second insulating layer is selectively disposed on the cell array region. A maximum thickness of the second insulating layer ranges from 1.5 times to 10 times a maximum thickness of the first insulating layer on the second insulating layer. The vertical channel structure includes an abrupt diameter change at a level of a top surface of the second insulating layer. The abrupt diameter change has a surface which is parallel to the top surface of the second insulating layer and is substantially coplanar with the top surface of the second insulating layer.

Abstract: A computer-implemented method includes: receiving, using a processor, multiple data session records (DSRs); storing the multiple DSRs in a memory communicatively coupled to the processor; analyzing, using the processor, the stored multiple DSRs for temporal and spatial data; and determining, using the processor, quality degradation by using the temporal and spatial data for the stored multiple DSRs.

Abstract: A three-dimensional semiconductor memory device includes; a first block and a second block arranged on a first substrate in a first direction, wherein each of the first block and the second block includes electrode layers stacked on the first substrate, a source layer interposed between the first block and the first substrate, and between the second block and the first substrate, a first insulating separation pattern interposed between the first block and the second block and extending in the first direction, wherein the first insulating separation pattern includes a line portion and a protruding portion, the line portion extending in a second direction crossing the first direction, and the protruding portion having a width greater than a width of the line portion, a first source contact plug penetrating the protruding portion of the first insulating separation pattern to electrically connect the source layer, and at least one through via penetrating the source layer and at least one of the first block and th

Abstract: In a 3D semiconductor memory device, a stack structure includes electrodes and first insulating layers disposed between the electrodes. The stack structure has a stair structure on a connection region. A vertical channel structure penetrates the stack structure on a cell array region. A vertical dummy structure penates the stair structure on the connection region. A second insulating layer is selectively disposed on the cell array region. A maximum thickness of the second insulating layer ranges from 1.5 times to 10 times a maximum thickness of the first insulating layer on the second insulating layer. The vertical channel structure includes an abrupt diameter change at a level of a top surface of the second insulating layer. The abrupt diameter change has a surface which is parallel to the top surface of the second insulating layer and is substantially coplanar with the top surface of the second insulating layer.

Abstract: A computer-implemented method includes: receiving, using a processor, multiple data session records (DSRs); storing the multiple DSRs in a memory communicatively coupled to the processor; analyzing, using the processor, the stored multiple DSRs for temporal and spatial data; and determining, using the processor, quality degradation by using the temporal and spatial data for the stored multiple DSRs.

Abstract: In a 3D semiconductor memory device, a stack structure includes electrodes and first insulating layers disposed between the electrodes. The stack structure has a stair structure on a connection region. A vertical channel structure penetrates the stack structure on a cell array region. A vertical dummy structure penates the stair structure on the connection region. A second insulating layer is selectively disposed on the cell array region. A maximum thickness of the second insulating layer ranges from 1.5 times to 10 times a maximum thickness of the first insulating layer on the second insulating layer. The vertical channel structure includes an abrupt diameter change at a level of a top surface of the second insulating layer. The abrupt diameter change has a surface which is parallel to the top surface of the second insulating layer and is substantially coplanar with the top surface of the second insulating layer.

Abstract: A display device includes a first substrate, a flexible printed circuit, and a film. The flexible printed circuit is disposed on a first area of the first substrate. The film is disposed on the first substrate and the flexible printed circuit. The flexible printed circuit includes a second substrate, a pad area, and a dummy pad. The pad area comprises pads disposed on the second substrate. The pads extend in a first direction and are spaced apart from one another in a second direction crossing the first direction. The dummy pad is disposed on the second substrate. The dummy pad is spaced apart from the pad area.

Abstract: A flexible touch sensing unit includes a substrate including a plane region and a bending region, a plurality of sensing electrodes disposed on the substrate, a plurality of sensing lines surrounding the plurality of sensing electrodes and electrically connected to the plurality of sensing electrodes, and a damage prevention layer disposed in the bending region. Cracks on the sensing electrodes and the sensing lines which are disposed in the bending region may be prevented by the damage prevention layer in the bending region. A resulting flexible display device using the flexible touch sensing unit may be thinner by omission of a flexibility enhancing layer.

Abstract: A display device including a first film, a flexible printed circuit, and a second film. The first film includes a substrate and a non-adhesive pattern, where the substrate includes a first area and a second area adjacent to the first area, and the non-adhesive pattern is formed on at least a portion of the second area. The flexible printed circuit is disposed on the first area of the first film. The second film is disposed on the flexible printed circuit and the first film.

Abstract: Embodiments of the present invention may involve a method, system, and computer program product for controlling privacy in a face recognition application. A computer may receive an input including a face recognition query and a digital image of a face. The computer may identify a target user associated with a facial signature in a first database based at least in part on a statistical correlation between a detected facial signature and one or more facial signatures in the first database. The computer may extract a profile of the target user from a second database. The profile of the target user may include one or more privacy preferences. The computer may generate a customized profile of the target user. The customized profile may omit one or more elements of the profile of the target user based on the one or more privacy preferences and/or a current context.

Abstract: A touch screen panel includes a substrate, sensing electrodes, outer wirings, contact units, and at least one dummy pattern. The substrate includes an active region and a non-active region, the non-active region disposed outside the active region. The sensing electrodes are disposed in the active region. The outer wirings are disposed in the non-active region. Each of the outer wirings is connected to a respective group of the sensing electrodes. The contact units connect the respective groups of sensing electrodes to the outer wirings. The at least one dummy pattern is disposed between adjacent contact units of the contact units.

Abstract: According to one exemplary embodiment, a method for time-shifted uploading of a data file through a backhaul network to a backend provider is provided. The method may include intercepting an upload request from an originating user located at a network edge. The method may include caching the data file associated with the upload request upstream of the backhaul network. This method may include uploading a placeholder file to the backend provider. The method may include receiving a file ID from the backend provider. The method may include mapping the received file ID to the cached data file. The method may include intercepting a request to access the data file by a requesting user. The method may include sending the requesting user the cached data file. The method may include uploading a copy of the data file to the backend provider based on a backhaul utilization policy.

Abstract: Various embodiments manage service issues within a wireless communication network. In one embodiment, a one or more call detail records associated with a set of wireless communication devices of a wireless communication network is received. A set of information within each of the one or more call detail records is compared to a baseline statistical model. The baseline statistical model identifies a normal operating state of the wireless communication network. At least one outlier call detail record in the one or more call detail records is identified based on the comparison. The at least one outlier call detail record indicates that at least one wireless communication device associated with the at least one outlier call detail record experienced one or more service issues.

Abstract: Systems, methods and computer program products for aliasing of named data objects (in named data networks) and entities for named data networks (e.g., named graphs for named data networks). In various examples, aliasing of named data objects may be implemented in one or more named data networks in the form of systems, methods and/or algorithms. In other examples, named graphs may be implemented in one or more named data networks in the form of systems, methods and/or algorithms.

Abstract: Embodiments of the present invention may involve a method, system, and computer program product for controlling privacy in a face recognition application. A computer may receive an input including a face recognition query and a digital image of a face. The computer may identify a target user associated with a facial signature in a first database based at least in part on a statistical correlation between a detected facial signature and one or more facial signatures in the first database. The computer may extract a profile of the target user from a second database. The profile of the target user may include one or more privacy preferences. The computer may generate a customized profile of the target user. The customized profile may omit one or more elements of the profile of the target user based on the one or more privacy preferences and/or a current context.

Abstract: Embodiments of the present invention may involve a method, system, and computer program product for controlling privacy in a face recognition application. A computer may receive an input including a face recognition query and a digital image of a face. The computer may identify a target user associated with a facial signature in a first database based at least in part on a statistical correlation between a detected facial signature and one or more facial signatures in the first database. The computer may extract a profile of the target user from a second database. The profile of the target user may include one or more privacy preferences. The computer may generate a customized profile of the target user. The customized profile may omit one or more elements of the profile of the target user based on the one or more privacy preferences and/or a current context.

Abstract: There is provided a method, a system and a computer program product for improving performance and fairness in sharing a cluster of dynamically available computing resources among multiple jobs. The system collects at least one parameter associated with availability of a plurality of computing resources. The system calculates, based on the collected parameter, an effective processing time each computing resource can provide to each job. The system allocates, based on the calculated effective processing time, the computing resources to the multiple jobs, whereby the multiple jobs are completed at a same time or an approximate time.

Abstract: A display device including a first film, a flexible printed circuit, and a second film. The first film includes a substrate and a non-adhesive pattern, where the substrate includes a first area and a second area adjacent to the first area, and the non-adhesive pattern is formed on at least a portion of the second area. The flexible printed circuit is disposed on the first area of the first film. The second film is disposed on the flexible printed circuit and the first film.