Abstract: Provided are a timing controller, and a driving method and a display device thereof. The timing controller may include a detection circuit and a control circuit. The detection circuit may detect a symbol error rate of a drive signal transmitted from a control circuit to a source drive circuit, and send the symbol error rate to the control circuit. The control circuit may automatically adjust a voltage swing of the drive signal according to the symbol error rate of the drive signal, and may enable a magnitude of the adjusted voltage swing to negatively correlate with a magnitude of the symbol error rate. Therefore, electromagnetic interference is effectively reduced, and flexibility in reducing electromagnetic interference is improved.

Abstract: A method and a device for driving a display panel, and a display device are provided. The method includes: dividing the display panel into at least two display regions, where each display region corresponds to a timing controller, and the timing controller is configured to control the corresponding display region to display; dividing each display region into multiple detection blocks; detecting whether a defect block exists in each display region; and enabling, when the defect block exists in only one display region, by the timing controller corresponding to the only one display region, a pattern detection function, and enabling, when the defect block exists in each of more than one display region, by the timing controllers corresponding to the more than one display region simultaneously, the pattern detection function.

Abstract: A method and a device for driving a display panel, and a display device are provided. The method includes: dividing the display panel into at least two display regions, where each display region corresponds to a timing controller, and the timing controller is configured to control the corresponding display region to display; dividing each display region into multiple detection blocks; detecting whether a defect block exists in each display region; and enabling, when the defect block exists in only one display region, by the timing controller corresponding to the only one display region, a pattern detection function, and enabling, when the defect block exists in each of more than one display region, by the timing controllers corresponding to the more than one display region simultaneously, the pattern detection function.

Abstract: A shift register, a method for driving the same, a gate driver circuit, and a display device are provided. The shift register includes an input circuit, a reset circuit, a first control circuit, a first output circuit, and a second output circuit, where the first output circuit includes two output channels, where one channel is that under the joint control of signals of a first clock signal terminal and a first node, a signal of a first clock signal terminal is provided to a drive signal output terminal of the shift register, and the other channel is that under the joint control of signals of the second clock signal terminal and the first node, a signal of a second clock signal terminal is provided to the drive signal output terminal.

Abstract: Provided are a timing controller, and a driving method and a display device thereof. The timing controller may include a detection circuit and a control circuit. The detection circuit may detect a symbol error rate of a drive signal transmitted from a control circuit to a source drive circuit, and send the symbol error rate to the control circuit. The control circuit may automatically adjust a voltage swing of the drive signal according to the symbol error rate of the drive signal, and may enable a magnitude of the adjusted voltage swing to negatively correlate with a magnitude of the symbol error rate. Therefore, electromagnetic interference is effectively reduced, and flexibility in reducing electromagnetic interference is improved.

Abstract: This disclosure discloses a shift register, a method for driving the same, a gate driver circuit, and a display device. The shift register includes an input circuit, a reset circuit, a first control circuit, a first output circuit, and a second output circuit, where the first output circuit includes two output channels, where one channel is that under the joint control of signals of a first clock signal terminal and a first node, a signal of a first clock signal terminal is provided to a drive signal output terminal of the shift register, and the other channel is that under the joint control of signals of the second clock signal terminal and the first node, a signal of a second clock signal terminal is provided to the drive signal output terminal, and the first output circuit cooperates with the other four circuits so that these two channels can operate alternately to thereby avoid current from flowing through only one of the channels so as to improve the service lifetime of the shift register.