Abstract: Techniques and architecture are disclosed for a method for making a custom circuit comprising forming a common wafer template, selecting at least two elements of the common wafer template to be chosen elements, and adding at least one metal layer to interconnect the chosen elements to form a circuit. The common wafer template includes a plurality of transistors, a plurality of resistors, a plurality of capacitors, and a plurality of bond pads. Final circuit customization of the common wafer template is accomplished by adding at least one metal layer that forms interconnects to passive and active elements in the template in order to complete the circuit.

Abstract: Techniques and architecture are disclosed for a method for making a custom circuit comprising forming a common wafer template, selecting at least two elements of the common wafer template to be chosen elements, and adding at least one metal layer to interconnect the chosen elements to form a circuit. The common wafer template includes a plurality of transistors, a plurality of resistors, a plurality of capacitors, and a plurality of bond pads. Final circuit customization of the common wafer template is accomplished by adding at least one metal layer that forms interconnects to passive and active elements in the template in order to complete the circuit.

Abstract: A GaN on diamond wafer and method for manufacturing the same is provided. The method comprising: disposing a GaN device or wafer on a substrate, having a nucleation layer disposed between the substrate and a GaN layer; affixing the device to a handling wafer; removing the substrate and substantially all the nucleation layer; and bonding the GaN layer to a diamond substrate.

Abstract: A GaN on diamond wafer and method for manufacturing the same is provided. The method comprising: disposing a GaN device or wafer on a substrate, having a nucleation layer disposed between the substrate and a GaN layer; affixing the device to a handling wafer; removing the substrate and substantially all the nucleation layer; and bonding the GaN layer to a diamond substrate.

Abstract: A field effect transistor and method for making such a transistor is provided, the field effect transistor comprising: a gate layer stack comprising a layer of a first metal is disposed proximate to at least one layer of a second metal, wherein the first metal alloys with the second metal to form a shape memory alloy. The shape metal allow may be NiTi, and at the contact plane between the layers, the alloy is formed when the transistor is heated to an elevated temperature.

Abstract: In summary, a vertical metalized transition in the form of a via goes from the back side of a high thermal conductivity substrate and through any semiconductor layers thereon to a patterned metalized strip, with the substrate having a patterned metalized layer on the back side that is provided with a keep away zone dimensioned to provide impedance matching for RF energy coupled through the substrate to the semiconductor device while at the same time permitting the heat generated by the semiconductor device to flow through the high thermal conductivity substrate, through the back side of the substrate and to a beat sink.

Abstract: A high power amplifier architecture is disclosure. One example configuration includes a first plurality of distributed amplification stages operatively coupled in a first string. A conductive trace associated with the first string provides a stepped structure, such that the associated inductance successively decreases from input to output of the first string. A second plurality of distributed amplification stages is operatively coupled in a second string, and a conductive trace associated therewith provides a stepped structure, such that the associated inductance successively decreases from input to output of the second string. In one example case, each of the first and second strings comprises gallium nitride transistor amplification stages formed on silicon carbide. The module may further include a heat spreader material that thermally and electrically couples to the amplification stages. The conductive trace associated with one string can be shared with another string.

Abstract: In summary, a vertical metalized transition in the form of a via goes from the back side of a high thermal conductivity substrate and through any semiconductor layers thereon to a patterned metalized strip, with the substrate having a patterned metalized layer on the back side that is provided with a keep away zone dimensioned to provide impedance matching for RF energy coupled through the substrate to the semiconductor device while at the same time permitting the heat generated by the semiconductor device to flow through the high thermal conductivity substrate, through the back side of the substrate and to a beat sink.

Abstract: A method for fabrication of a field effect transistor gate, with or without field plates, includes the steps of defining a relatively thin Schottky metal layer by a lithography/metal liftoff or metal deposition/etch process on a semiconductor surface. This is followed by depositing a dielectric passivation layer over the entire wafer and defining a second lithographic pattern coincident with or slightly inset from the boundaries of the previously defined metal gate layer. This is followed by etching the dielectric using dry or wet etching techniques and stripping the resist, followed by exposing and developing a third resist pattern to define the thicker gate metal layers required for electrical conductivity and also for the field plate if one is utilized. The final step is depositing gate and/or field plate metal, resulting in a gate electrode and an integral field plate.

Abstract: A high power amplifier architecture is disclosure. One example configuration includes a first plurality of distributed amplification stages operatively coupled in a first string. A conductive trace associated with the first string provides a stepped structure, such that the associated inductance successively decreases from input to output of the first string. A second plurality of distributed amplification stages is operatively coupled in a second string, and a conductive trace associated therewith provides a stepped structure, such that the associated inductance successively decreases from input to output of the second string. In one example case, each of the first and second strings comprises gallium nitride transistor amplification stages formed on silicon carbide. The module may further include a heat spreader material that thermally and electrically couples to the amplification stages. The conductive trace associated with one string can be shared with another string.

Abstract: An etched grooved GaN-based permeable-base transistor structure is disclosed, along with a method for fabrication of same.

Abstract: A method for fabrication of a field effect transistor gate, with or without field plates, includes the steps of defining a relatively thin Schottky metal layer by a lithography/metal liftoff or metal deposition/etch process on a semiconductor surface. This is followed by depositing a dielectric passivation layer over the entire wafer and defining a second lithographic pattern coincident with or slightly inset from the boundaries of the previously defined metal gate layer. This is followed by etching the dielectric using dry or wet etching techniques and stripping the resist, followed by exposing and developing a third resist pattern to define the thicker gate metal layers required for electrical conductivity and also for the field plate if one is utilized. The final step is depositing gate and/or field plate metal, resulting in a gate electrode and an integral field plate.

Abstract: A method for fabrication of a field effect transistor gate, with or without field plates, includes the steps of defining a relatively thin Schottky metal layer by a lithography/metal liftoff or metal deposition/etch process on a semiconductor surface. This is followed by depositing a dielectric passivation layer over the entire wafer and defining a second lithographic pattern coincident with or slightly inset from the boundaries of the previously defined metal gate layer. This is followed by etching the dielectric using dry or wet etching techniques and stripping the resist, followed by exposing and developing a third resist pattern to define the thicker gate metal layers required for electrical conductivity and also for the field plate if one is utilized. The final step is depositing gate and/or field plate metal, resulting in a gate electrode and an integral field plate.

Abstract: A method for fabrication of a field effect transistor gate, with or without field plates, includes the steps of defining a relatively thin Schottky metal layer by a lithography/metal liftoff or metal deposition/etch process on a semiconductor surface. This is followed by depositing a dielectric passivation layer over the entire wafer and defining a second lithographic pattern coincident with or slightly inset from the boundaries of the previously defined metal gate layer. This is followed by etching the dielectric using dry or wet etching techniques and stripping the resist, followed by exposing and developing a third resist pattern to define the thicker gate metal layers required for electrical conductivity and also for the field plate if one is utilized. The final step is depositing gate and/or field plate metal, resulting in a gate electrode and an integral field plate.

Abstract: A method for fabrication of a field effect transistor gate, with or without field plates, includes the steps of defining a relatively thin Schottky metal layer by a lithography/metal liftoff or metal deposition/etch process on a semiconductor surface. This is followed by depositing a dielectric passivation layer over the entire wafer and defining a second lithographic pattern coincident with or slightly inset from the boundaries of the previously defined metal gate layer. This is followed by etching the dielectric using dry or wet etching techniques and stripping the resist, followed by exposing and developing a third resist pattern to define the thicker gate metal layers required for electrical conductivity and also for the field plate if one is utilized. The final step is depositing gate and/or field plate metal, resulting in a gate electrode and an integral field plate.

Abstract: An etched grooved GaN-based permeable-base transistor structure is disclosed, along with a method for fabrication of same.

Abstract: An etched grooved GaN-based permeable-base transistor structure is disclosed, along with a method for fabrication of same.

Abstract: A photodetector (100, 200, 300) comprising a gallium nitride substrate, at least one active layer (104, 302) disposed on the substrate (102, 202, 306), and a conductive contact structure (106, 210, 308) affixed to the active layer (104, 302) and, in some embodiments, the substrate (102, 202, 306). The invention includes photodetectors (100, 200, 300) having metal-semiconductor-metal structures, P-i-N structures, and Schottky-barrier structures. The active layers (104, 302) may comprise Ga1-x-yAlxInyN1-z-w PzAsw, or, preferably, Ga1-xAlxN. The gallium nitride substrate comprises a single crystal gallium nitride wafer and has a dislocation density of less than about 105 cm?2. A method of making the photodetector (100, 200, 300) is also disclosed.

Abstract: An etched grooved GaN-based permeable-base transistor structure is disclosed, along with a method for fabrication of same.

Abstract: An etched grooved GaN-based permeable-base transistor structure is disclosed, along with a method for fabrication of same.