Abstract: A method and circuit for accurately detecting an output short circuit in a switching regulator. A first transistor and a second transistor are connected in series and driven in a complementary manner. A comparator compares output current, which is generated when the first and second transistors are driven, with a short circuit detection threshold to generate a first short circuit detection signal. A timing controller retrieves the first short circuit detection signal generated by the comparator at a predetermined time to generate a second short circuit detection signal.

Abstract: A circuit and a method for reducing output noise when a pulse width modulation mode is started. A pulse width modulation circuit generates a first pulse signal having a duty cycle that is in accordance with an output voltage of a regulator circuit. A drive circuit generates the output voltage from an input voltage in response to the first pulse signal provided from the pulse width modulation circuit. A feed forward circuit controls the pulse width modulation circuit in a manner to generate the first pulse signal having a duty cycle that maintains the output voltage at a desired level before the pulse width modulation circuit provides the first pulse signal to the drive circuit.

Abstract: A pulse width modulation circuit that controls the output voltage of a regulator. The regulator includes a switching element, which is activated and deactivated by a pulse signal, and a PMW control circuit, which provides the switching element with the pulse signal in accordance with a duty ratio determined from a reference voltage and an error voltage. The error voltage is the difference between the output voltage and reference voltage. The PWM control circuit includes a current source that generates a current in accordance with the error voltage, a capacitor arranged between the current source and ground, and a comparator. The comparator has a non-inverting input terminal, which is connected between the current source and capacitor, and an inverting input terminal, to which the reference voltage is applied. An output signal of the comparator is provided to the switching element.

Abstract: A semiconductor device semiconductor device allowing for use of a test circuit that withstands only low voltages and has a small circuit area. A high-voltage operational circuit, which is operated at a high voltage, is connected to first and second pads. A multiplexer used to test the high-voltage operational circuit is connected to a third pad in addition to the first and second pads. Fuses are arranged on wires connecting the first and second pads to the multiplexer. An inspection board connects the third pad to ground after testing the high-voltage operational circuit, provides a breakage signal to the multiplexer, and applies voltage to the first or second pad. The multiplexer, which receives the breakage signal, connects the first or second pad with the third pad so that current flows therebetween. This breaks the corresponding fuse and insulates the multiplexer from the high-voltage operational circuit.

Abstract: A pulse width modulation (PWM) wave output circuit that efficiently and accurately outputs dual PWM waves includes two comparators, an OR circuit, and an AND circuit. A voltage generator supplies the comparators with ramp voltages having the same wave height and shifted phases. The comparator compares the ramp voltages with the reference voltage and provides the comparison results to the OR circuit and the AND circuit. The OR circuit outputs a first modulation wave, and the AND circuit generates a second modulation wave. Accordingly, modulation waves having different duties are output based on ramp voltage having different phases.

Abstract: A method and circuit for accurately detecting an output short circuit in a switching regulator. A first transistor and a second transistor are connected in series and driven in a complementary manner. A comparator compares output current, which is generated when the first and second transistors are driven, with a short circuit detection threshold to generate a first short circuit detection signal. A timing controller retrieves the first short circuit detection signal generated by the comparator at a predetermined time to generate a second short circuit detection signal.

Abstract: A circuit and a method for reducing output noise when a pulse width modulation mode is started. A pulse width modulation circuit generates a first pulse signal having a duty cycle that is in accordance with an output voltage of a regulator circuit. A drive circuit generates the output voltage from an input voltage in response to the first pulse signal provided from the pulse width modulation circuit. A feed forward circuit controls the pulse width modulation circuit in a manner to generate the first pulse signal having a duty cycle that maintains the output voltage at a desired level before the pulse width modulation circuit provides the first pulse signal to the drive circuit.

Abstract: A pulse width modulation (PWM) wave output circuit that efficiently and accurately outputs dual PWM waves includes two comparators, an OR circuit, and an AND circuit. A voltage generator supplies the comparators with ramp voltages having the same wave height and shifted phases. The comparator compares the ramp voltages with the reference voltage and provides the comparison results to the OR circuit and the AND circuit. The OR circuit outputs a first modulation wave, and the AND circuit generates a second modulation wave. Accordingly, modulation waves having different duties are output based on ramp voltage having different phases.

Abstract: An interface cell transmits a signal with a delay time corresponding to a delay time control signal. A delay time control circuit consists of a delay chain and a PLL circuit. The delay chain consists of a plurality of series-connected interface cells to a head cell of which a clock signal is supplied, and a delay signal of a clock signal is then fetched from the interface cell at an arbitrary stage. The PLL circuit generates a delay time control signal so as to make phase difference between the clock signal and the delay signal equal. This is true of a delay cell. A phase difference compensation circuit is provided on an output end of a clock line of the integrated circuit to delay an input clock signal based on an input control signal.

Abstract: A PLL circuit includes: a phase comparator for comparing the phase of an input signal with the phase of a reference input signal to output a signal according to the phase difference therebetween; a low pass filter for outputting a low frequency control voltage on the basis of the output of the phase comparator; a voltage control oscillator for controlling an oscillating frequency on the basis of the control voltage; and a characteristic control part for controlling the characteristic of oscillating frequency to control voltage of the voltage control oscillator on the basis of n+1 ranges of first through n+1-th ranges obtained by dividing a variable range of the control voltage by first through n-th (n≧2) thresholds which are different from each other. Thus, it is possible to widen the operating frequency range, and it is possible to inhibit the frequency variation due to noises.

Abstract: An interface cell transmits a signal with a delay time corresponding to a delay time control signal. A delay time control circuit consists of a delay chain and a PLL circuit. The delay chain consists of a plurality of series-connected interface cells to a head cell of which a clock signal is supplied, and a delay signal of a clock signal is then fetched from the interface cell at an arbitrary stage. The PLL circuit generates a delay time control signal so as to make phase difference between the clock signal and the delay signal equal. This is true of a delay cell. A phase difference compensation circuit is provided on an output end of a clock line of the integrated circuit to delay an input clock signal based on an input control signal.