Abstract: An information processing device includes: a plurality of processing units configured to execute software components each having a priority level; an abnormality determination unit configured to determine whether any one of the plurality of processing units has an abnormality; and a changing unit configured to, when the abnormality determination unit has determined that any one of the processing units has an abnormality, execute control such that the processing unit not determined to have an abnormality processes the software component supposed to be executed by the processing unit determined to have an abnormality. The changing unit is configured to process the software component having the priority level higher than or equal to a reference level among the software components supposed to be executed by the processing unit determined to have an abnormality.

Abstract: A system and method for providing a fault-tolerant basis to execute instructions is disclosed. The system comprises an error detector, a rewriting module, a recovery engine, a fault locator and a fallback programming module. The error detector detects a first error in the execution of an instruction in a faulty stage unit of a first pipeline unit. The rewriting module rewrites the instruction to form a rewritten instruction responsive to detecting the first error. The recovery engine executes the rewritten instruction in the first pipeline unit. The error detector determines if a second error occurs in the execution of the rewritten instruction. Responsive to detecting the second error, the recovery engine selects a substitute stage unit for the faulty stage unit from a second pipeline unit. The fault locator locates a faulty component for the faulty stage unit. The fallback programming module establishes a fallback unit for the faulty component.

Abstract: A system and method for providing a fault-tolerant basis to execute instructions is disclosed. The system comprises an error detector, a rewriting module, a recovery engine, a fault locator and a fallback programming module. The error detector detects a first error in the execution of an instruction in a faulty stage unit of a first pipeline unit. The rewriting module rewrites the instruction to form a rewritten instruction responsive to detecting the first error. The recovery engine executes the rewritten instruction in the first pipeline unit. The error detector determines if a second error occurs in the execution of the rewritten instruction. Responsive to detecting the second error, the recovery engine selects a substitute stage unit for the faulty stage unit from a second pipeline unit. The fault locator locates a faulty component for the faulty stage unit. The fallback programming module establishes a fallback unit for the faulty component.

Abstract: During an erasing sequence, after a preprogram operation (S1), an erasing operation (S3), and an APDE operation (S5) are executed and confirmation by an APDE verify operation (S6: P) and confirmation by an erase-verify operation (S7: P) are completed, step A is executed prior to a soft-program operation (S10) of a plurality of memory cells. A dummy memory cell program operation (S8) is continuously executed until a completion of a program operation is confirmed by a dummy memory cell program verify operation (S9). By execution of the program operation on the dummy memory cells, a voltage stress similar to that of a program operation is applied to memory cells in an over-erased state via bit lines. Thereby, the over-erased state is reduced thereby lowering a column leak current. Erroneous recognition during a soft-program verify operation (S11) can be prevented, and excessive soft-programming can be avoided.

Abstract: During an erasing sequence, after a preprogram operation (S1), an erasing operation (S3), and an APDE operation (S5) are executed and confirmation by an APDE verify operation (S6: P) and confirmation by an erase-verify operation (S7: P) are completed, step A is executed prior to a soft-program operation (S10) of a plurality of memory cells. A dummy memory cell program operation (S8) is continuously executed until a completion of a program operation is confirmed by a dummy memory cell program verify operation (S9). By execution of the program operation on the dummy memory cells, a voltage stress similar to that of a program operation is applied to memory cells in an over-erased state via bit lines. Thereby, the over-erased state is reduced thereby lowering a column leak current. Erroneous recognition during a soft-program verify operation (S11) can be prevented, and excessive soft-programming can be avoided.