Abstract: An integrated circuit device includes a support substrate, a first semiconductor chip and a second semiconductor chip provided on the support substrate, and a connection member made of solder. The first semiconductor chip and the second semiconductor chip each includes a semiconductor substrate, an interconnect layer provided on the semiconductor substrate, and a pad provided on a side surface of the interconnect layer. The connection member contacts a side surface of the pad of the first semiconductor chip and a side surface of the pad of the second semiconductor chip.

Abstract: An integrated circuit device includes a support substrate, a first semiconductor chip and a second semiconductor chip provided on the support substrate, and a connection member made of solder. The first semiconductor chip and the second semiconductor chip each includes a semiconductor substrate, an interconnect layer provided on the semiconductor substrate, and a pad provided on a side surface of the interconnect layer. The connection member contacts a side surface of the pad of the first semiconductor chip and a side surface of the pad of the second semiconductor chip.

Abstract: A semiconductor device including a memory cell having a memory transistor and select gate transistor and a peripheral transistor is disclosed. The memory transistor has a stacked gate structure formed by sequentially stacking a gate insulating film, first gate electrode, inter-poly insulating film, and second gate electrode on a semiconductor substrate. The select gate transistor has a stacked gate structure identical to the memory transistor, and selects the memory transistor. The peripheral transistor forms a peripheral circuit of the memory cell, and has a gate electrode having a single-layer structure. A through hole reaching the first gate electrode is formed in the second gate electrode and inter-poly insulating film positioned on an element isolation film of the select gate transistor. A contact plug buried in this through hole electrically connects the second gate electrode and first gate electrode.

Abstract: A nonvolatile semiconductor memory according to an example of the present invention is provided with a memory cell having a floating gate electrode and a control gate electrode, and a select gate transistor having a select gate electrode and connected in series to the memory cell. A cell unit is comprised with the memory cell and the select gate transistor. A bird's beak of the edge at the memory cell side of the select gate electrode is larger than a bird's beak of at least one edge of the floating gate electrode.

Abstract: A semiconductor device including a memory cell having a memory transistor and select gate transistor and a peripheral transistor is disclosed. The memory transistor has a stacked gate structure formed by sequentially stacking a gate insulating film, first gate electrode, inter-poly insulating film, and second gate electrode on a semiconductor substrate. The select gate transistor has a stacked gate structure identical to the memory transistor, and selects the memory transistor. The peripheral transistor forms a peripheral circuit of the memory cell, and has a gate electrode having a single-layer structure. A through hole reaching the first gate electrode is formed in the second gate electrode and inter-poly insulating film positioned on an element isolation film of the select gate transistor. A contact plug buried in this through hole electrically connects the second gate electrode and first gate electrode.

Abstract: A nonvolatile semiconductor memory according to an example of the present invention is provided with a memory cell having a floating gate electrode and a control gate electrode, and a select gate transistor having a select gate electrode and connected in series to the memory cell. A cell unit is comprised with the memory cell and the select gate transistor. A bird's beak of the edge at the memory cell side of the select gate electrode is larger than a bird's beak of at least one edge of the floating gate electrode.

Abstract: An inorganic film with a double-layers structure is used as an etching mask in an EEPROM area to pattern a double-layers gate, while a thin inorganic film obtained by removing one layer of the double-layers inorganic film by etching is used as an etching mask in a CMOS logic circuit area. Therefore, the gate pattern can be formed with high precision by using a thin etching mask in the CMOS logic circuit area.

Abstract: There is provided a semiconductor memory device using a three-layer gate electrode material film to improve yields and reliability, and a method for producing the same. A floating gate 4 of a memory transistor MT is formed of a first-layer gate electrode material film L1, and a control gate 6 is formed of a laminated film of second-layer and third-layer gate electrode material films L2 and L3. A gate electrode 8 of a selecting gate transistor ST is formed of the first-layer gate electrode material film L1, and the second-layer and third-layer gate electrode material films L2 and L3 which are stacked thereon via an interlayer dielectric film 5. The third-layer gate electrode material film L3 contacts the first-layer gate electrode material film L1 via an opening 9. A gate electrode 12 of a peripheral circuit transistor Q is formed of the laminated film of the second-layer and third-layer gate electrode material films L2 and L3.