Abstract: A semiconductor device according to one embodiment of the present invention includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate through a gate insulating film; an elevated source/drain region formed away from the gate electrode, a surface of the elevated source/drain region being higher than that of the semiconductor substrate; a source/drain extension region formed in the semiconductor substrate lying under a recess portion formed between the gate electrode and the elevated source/drain region; a first gate sidewall insulating film formed on a side face of the gate electrode, and on a bottom face and a side face of the recess portion; and a second gate sidewall insulating film formed on the first gate sidewall insulating film.

Abstract: A semiconductor device has a first and a second semiconductor layer provided on an insulating film on a support substrate. A first memory cell transistor, which constitutes a part of a memory cell in an SRAM, has a first gate electrode of a first conductivity type and first source/drain diffusion layers of a second conductivity type opposite to the first conductivity type. The following expression is fulfilled the thickness of the first conductivity type?one-third of a length of the first gate electrode in its channel length. A first peripheral transistor, which constitutes a part of a peripheral circuit, has a third gate electrode and a third source/drain diffusion layers. The following expression is satisfied the thickness of the second semiconductor layer>one-third of a length of the third gate electrode in its channel length direction.

Abstract: According to the present invention, there is provided a semiconductor device comprising: a gate electrode formed on a surface of a semiconductor device via a gate insulating film; gate electrode sidewalls formed on side surfaces of said gate electrode; a first source region and first drain region formed, in a surface portion of said semiconductor substrate, below said gate electrode sidewalls on two sides of a channel region positioned below said gate electrode; a second source region formed adjacent to a side, which is opposite to said channel region, of said first source region, and having a junction depth larger than that of said first source region, and a second rain region formed adjacent to a side, which is opposite to said channel region, of said first drain region, and having a junction depth larger than that of said first drain region; and a layer formed to a region deeper than said first source region and first drain region on the two sides of said channel region so as to sandwich said channel regio

Abstract: A semiconductor device has a first and a second semiconductor layer provided on an insulating film on a support substrate. A first memory cell transistor, which constitutes a part of a memory cell in an SRAM, has a first gate electrode of a first conductivity type and first source/drain diffusion layers of a second conductivity type opposite to the first conductivity type. The following expression is fulfilled the thickness of the first conductivity type≦one-third of a length of the first gate electrode in its channel length. A first peripheral transistor, which constitutes a part of a peripheral circuit, has a third gate electrode and a third source/drain diffusion layers. The following expression is satisfied the thickness of the second semiconductor layer>one-third of a length of the third gate electrode in its channel length direction.