Abstract: A circuit comprises an H-bridge circuit that includes a pair of current sources and a plurality of transistors. The H-bridge circuit includes a first output and a second output. One of the current sources is coupled to receive a supply voltage. A control circuit is configured to control, based on a sum of voltages on the first and second outputs, current of at least one of the current sources through at least some of the plurality of transistors.

Abstract: A circuit comprises an H-bridge circuit that includes a pair of current sources and a plurality of transistors. The H-bridge circuit includes a first output and a second output. One of the current sources is coupled to receive a supply voltage. A control circuit is configured to control, based on a sum of voltages on the first and second outputs, current of at least one of the current sources through at least some of the plurality of transistors.

Abstract: A temperature-compensated ring oscillator circuit includes a plurality of series-coupled inverters in a ring configuration and a plurality of capacitors. Each capacitor couples to an output of a corresponding inverter. A first transistor is included that comprises a first control input and first and second current terminals. The second current terminal couples to the power supply terminal of each inverter. A second transistor is included that comprises a second control input and third and fourth current terminals. A resistor couples to the fourth current terminal of the second transistor at a first node. An amplifier includes a first amplifier input, a second amplifier input, and an amplifier output. The amplifier output couples to the first and second control inputs. The first amplifier input couples to the second current terminal of the first transistor and the second amplifier input couples to the first node.

Abstract: A delay compensated comparator circuit is disclosed. The circuit includes an amplifier circuit having a first input terminal coupled to receive a reference signal and having a second input terminal and a first output terminal. A capacitor is arranged to couple an input signal to the second input terminal. A resistor is coupled between the first output terminal and the second input terminal. A comparator circuit has a third input terminal coupled to receive the input signal, a fourth input terminal coupled to the first output terminal, and a second output terminal.

Abstract: A method and device for input offset cancellation utilizing a latched comparator that is configurable as a linear amplifier capable of sampling and cancelling offset in the inputs to the latched comparator. The latched comparator is configured according to three control signals for operation in three operating intervals. During a first operating interval, the latched comparator is configured as a linear amplifier that samples the offset at the inputs to the latched comparator. Based on the sampled offset, the linear amplifier cancels the offset in the inputs to the latched comparator. During a second operating interval, the latched comparator reverts to operation as comparator and the inputs to the latch are reset. During a third interval, the latch resolves the inputs to the comparator and generates an output signal indicating.

Abstract: A delay compensated comparator circuit is disclosed. The circuit includes an amplifier circuit having a first input terminal coupled to receive a reference signal and having a second input terminal and a first output terminal. A capacitor is arranged to couple an input signal to the second input terminal. A resistor is coupled between the first output terminal and the second input terminal. A comparator circuit has a third input terminal coupled to receive the input signal, a fourth input terminal coupled to the first output terminal, and a second output terminal.

Abstract: A method and device for input offset cancellation utilizing a latched comparator that is configurable as a linear amplifier capable of sampling and cancelling offset in the inputs to the latched comparator. The latched comparator is configured according to three control signals for operation in three operating intervals. During a first operating interval, the latched comparator is configured as a linear amplifier that samples the offset at the inputs to the latched comparator. Based on the sampled offset, the linear amplifier cancels the offset in the inputs to the latched comparator. During a second operating interval, the latched comparator reverts to operation as comparator and the inputs to the latch are reset. During a third interval, the latch resolves the inputs to the comparator and generates an output signal indicating.

Abstract: A method and device for input offset cancellation utilizing a latched comparator that is configurable as a linear amplifier capable of sampling and cancelling offset in the inputs to the latched comparator. The latched comparator is configured according to three control signals for operation in three operating intervals. During a first operating interval, the latched comparator is configured as a linear amplifier that samples the offset at the inputs to the latched comparator. Based on the sampled offset, the linear amplifier cancels the offset in the inputs to the latched comparator. During a second operating interval, the latched comparator is configured to operate as comparator and the inputs to the latch are reset. During a third interval, the latch resolves the inputs to the comparator and generates an output signal indicating the relative values of the inputs.

Abstract: An adaptive driver includes a gate driver having at least one driving transistor for driving a control node of switching transistor(s) that includes an output node (OUT) which provides Vout. An adjustable current source is in series with the driving transistor, a high pass filter (HPF) is between OUT and ground for detecting a slew rate of the switching transistor and outputting a voltage pulse (Vslp) output having a peak voltage amplitude at least monotonically reflecting a slope of Vout during switching. Detection signal processing circuitry is coupled to the output of the HPF for processing Vslp and slew rate control circuitry has an input coupled to the output of the detection signal processing circuitry. The output of the slew rate control circuitry is coupled to the current source for controlling its current level for changing the slew rate of the switching transistor to provide a desired slew rate range.

Abstract: An adaptive driver includes a gate driver having at least one driving transistor for driving a control node of switching transistor(s) that includes an output node (OUT) which provides Vout. An adjustable current source is in series with the driving transistor, a high pass filter (HPF) is between OUT and ground for detecting a slew rate of the switching transistor and outputting a voltage pulse (Vslp) output having a peak voltage amplitude at least monotonically reflecting a slope of Vout during switching. Detection signal processing circuitry is coupled to the output of the HPF for processing Vslp and slew rate control circuitry has an input coupled to the output of the detection signal processing circuitry. The output of the slew rate control circuitry is coupled to the current source for controlling its current level for changing the slew rate of the switching transistor to provide a desired slew rate range.

Abstract: A method and device for input offset cancellation utilizing a latched comparator that is configurable as a linear amplifier capable of sampling and cancelling offset in the inputs to the latched comparator. The latched comparator is configured according to three control signals for operation in three operating intervals. During a first operating interval, the latched comparator is configured as a linear amplifier that samples the offset at the inputs to the latched comparator. Based on the sampled offset, the linear amplifier cancels the offset in the inputs to the latched comparator. During a second operating interval, the latched comparator is configured to operate as comparator and the inputs to the latch are reset. During a third interval, the latch resolves the inputs to the comparator and generates an output signal indicating the relative values of the inputs.

Abstract: A Universal Serial Bus (USB) switch matrix is provided. The switch matrix generally comprises a switch network, and amplifier, a adjustable current source, and variable resistors. The switch network is able to output a differential output signal and a common mode signal. The amplifier compares the common mode signal to a reference voltage, and the amplifier adjusts the magnitude of the current from the adjustable current source and the resistances of the variable resistors based at least in part on the comparison to adjust the peak-to-peak voltage swing of the output signal.

Abstract: A Universal Serial Bus (USB) switch matrix is provided. The switch matrix generally comprises a switch network, and amplifier, a adjustable current source, and variable resistors. The switch network is able to output a differential output signal and a common mode signal. The amplifier compares the common mode signal to a reference voltage, and the amplifier adjusts the magnitude of the current from the adjustable current source and the resistances of the variable resistors based at least in part on the comparison to adjust the peak-to-peak voltage swing of the output signal.

Abstract: Subtraction of a signal 111 from a pulse response 110, where signal 111 provides a good approximation of the tail of pulse response 110, can provide a method for canceling the tail of pulse response 110. For continuous data streams, signals X(t), 223 and Y(t) can correspond to, respectively, signals 110, 111 and 112. X(t) differs from 110 in being a continuous data stream. 223 differs from 111 in being the low pass filtering of X(t), such low pass filtering accomplished by a unit LPF 211. Y(t) differs from 112 in being a continuous stream of equalized data, produced by subtracting the signal at 223 from X(t). A measurement unit 213, analysis unit 214 and decision unit 215 can act to continuously adapt LPF 211 such that tail cancellation equalization is continuously achieved. Measurement unit 213 can construct, from Y(t), a set of correlation measurements that can be used to adapt LPF 211.

Abstract: A receiver system (10) includes a first stage of modulation (46, 51) which modulates a radio-frequency input signal (17), and a second stage of modulation (56, 61, 66, 71) which modulates outputs from the first stage. Combining circuits (76, 77) combine selected outputs of the second stage to produce two outputs (18, 19) from the receiver system. The first stage receives modulating signals (22, 23) from a first oscillator (21), and the second stage receives modulating signals (27, 28, 32, 33) from second and third oscillators (26, 31). The second and third oscillators each operate at a substantially lower frequency than the first oscillator. The phase difference between the modulating signals produced by each of the second and third oscillators is adjusted so that there is minimum image power in each of the system outputs (18, 19), even if the modulating signals from the first oscillator are not in phase quadrature.