Abstract: A system includes an electromechanical device coupled to a sensing device to detect input to the electromechanical device and display to displays information related to the electromechanical device. The sensing device includes a touch surface including tactile features delineating a portion of the touch surface to be touched by the conductive object. A sensor of the system is to detect the conductive object proximate to the delineated portion of the touch surface based on a capacitance.

Abstract: A capacitance sense device can include a plurality of sense electrodes; a nonconductive structure comprising first regions formed over the sense electrodes and second regions formed between first regions that are less compressible than the first regions; a conductive touch surface formed over the nonconductive structure; and a capacitance sense circuit coupled to at least the sense electrodes.

Abstract: A capacitance sense device can include a plurality of sense electrodes; a nonconductive structure comprising first regions formed over the sense electrodes and second regions formed between first regions that are less compressible than the first regions; a conductive touch surface formed over the nonconductive structure; and a capacitance sense circuit coupled to at least the sense electrodes.

Abstract: A static random-access memory (SRAM) provides volatile storage of data in a cellular telephone. Connected to the volatile SRAM is a second SRAM that provides nonvolatile storage of data by backup battery means. Writing and reading of either volatile or nonvolatile data can occur. Additionally, provision is made to automatically back up data written to the volatile SRAM in the nonvolatile SRAM, as well as to streamline restoration of backed-up data from the nonvolatile SRAM to the volatile SRAM.

Abstract: An apparatus for address selection including a first storage element and a second storage element coupled to an input bus. The first storage element stores a first address segment and the second storage element stores a second address segment upon the receipt of respective complementary clock signals. An internal address bus propagates the address segments together.

Abstract: A memory device (200) can include memory cell arrays (202-a and 202-b) accessed according to phase shifted clock signals. Memory cell array (202-a) can be accessed at double data rates essentially synchronous with clock signal CLK. Memory cell array (202-b) can be accessed at double data rates essentially synchronous with a phase delayed clock signal DCLK. Such an arrangement can provide eight data accesses (four reads and four writes) in a single clock cycle.

Abstract: A method and logic for providing an asynchronous interface to a synchronous memory is disclosed. One embodiment of the present invention provides for a memory having a first logical unit which is operable to generate a synchronized clock signal in response to a chip select signal to the memory. The memory comprises synchronous memory arrays. The synchronized clock signal is input to the selected synchronous memory array. This allows an access to the synchronous memory to complete within a timing budget of the asynchronous interface. Furthermore, the memory has a second logical unit which is operable, in response to the chip select signal and a second signal input to the memory, to put an input/output bus coupled to the synchronous memory into a high impedance state by the end of the memory access. The second input signal may be a read enable or a write enable signal.

Abstract: Embodiments of the present invention provide a memory device having multiple modes of data transfer. In one embodiment, async/sync logic and a configuration register provide for asynchronous and synchronous data transfer. The async/sync logic utilizes the configuration register and various control signals to determine whether a data transfer operation should be asynchronous or synchronous. The async/sync logic also utilizes the configuration register and various control signals to determine other functionalities of the particular data transfer mode. Functionalities may include normal and page mode, page length, bust read, linear or interleaved burst, burst wrap, burst suspend, data hold length, first access latency, transition between synchronous and asynchronous mode, and the like.

Abstract: A termination circuit for use on a conductor of a transmission line. The termination circuit generally comprises a first, second, third and fourth transistor. The first transistor may have (i) a first drain node couplable to the conductor, (ii) a first source node couplable to a first power source presenting a first reference voltage, and (iii) a first gate node. The second transistor may have (i) a second drain node couplable to the conductor, (ii) a second source node couplable to a second power source presenting a second reference voltage, and (iii) a second gate node. The third transistor (i) may have a third source node coupled to the first gate node and (ii) may be configured to bias the first gate node to a first voltage below the first reference voltage. The fourth transistor (i) may have a fourth source node coupled to the second gate node and (ii) may be configured to bias the second gate node to a second voltage above the second reference voltage.

Abstract: A termination circuit for use on a conductor of a transmission line. The termination circuit generally comprises a first, second, third and fourth transistor. The first transistor may have (i) a first drain node couplable to the conductor, (ii) a first source node couplable to a first power source presenting a first reference voltage, and (iii) a first gate node. The second transistor may have (i) a second drain node couplable to the conductor, (ii) a second source node couplable to a second power source presenting a second reference voltage, and (iii) a second gate node. The third transistor (i) may have a third source node coupled to the first gate node and (ii) may be configured to bias the first gate node to a first voltage below the first reference voltage. The fourth transistor (i) may have a fourth source node coupled to the second gate node and (ii) may be configured to bias the second gate node to a second voltage above the second reference voltage.