Patents by Inventor Kanshi Abe

Kanshi Abe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7535077
    Abstract: A semiconductor device having a semiconductor substrate includes an active region for forming transistors in which a gate is installed. An element isolation region for isolating each of transistors from others includes an ASTI structure. A stress region is located at the interface with the element isolation region within the active region. In the stress region, a potential stress caused by the difference between a material for the element isolation region and a material of the semiconductor substrate is generated, so that a first impurity region for a source and/or a drain is formed in the active region in which the gate is not formed and/or forming the element isolation region. A first impurity region at least includes a first impurity for a source and/or a drain, which is formed in the active region except the stress region and the gate. A second ion impurity region includes a second impurity, each of which mass is smaller than the first impurity, at least in a region having the stress region.
    Type: Grant
    Filed: July 2, 2007
    Date of Patent: May 19, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Kanshi Abe
  • Publication number: 20070252222
    Abstract: A method of manufacturing a semiconductor device having a semiconductor substrate that includes an active region for forming transistor elements, which includes a gate, and an element isolation region for isolating the transistor elements separately each other, which has a STI structure, the method comprises; first—ion implanting first ions onto the surface of the semiconductor substrate in a region other than a stress region in the active region, which is located at the interface with the element isolation region, in the stress region, a potential stress is generated by forming the element isolation region and/or the difference between a material of the element isolation region and a material of the semiconductor substrate, so that a first impurity region for a source and/or a drain is formed in the active region in which the gate is not formed; and second-ion implanting second ions each of which mass is smaller than that of each of the first ions so that a second ion impurity region is formed in the stress
    Type: Application
    Filed: July 2, 2007
    Publication date: November 1, 2007
    Inventor: Kanshi Abe
  • Patent number: 7253067
    Abstract: A method of manufacturing a semiconductor device having a semiconductor substrate that includes an active region for forming transistor elements, which includes a gate, and an element isolation region for isolating the transistor elements separately each other, which has a STI structure, the method comprises; first—ion implanting fist ions onto the surface of the semiconductor substrate in a region other than a stress region in the active region, which is located at the interface with the element isolation region, in the stress region, a potential stress is generated by forming the element isolation region and/or the difference between a material of the element isolation region and a material of the semiconductor substrate, so that a first impurity region for a source and/or a drain is formed in the active region in which the gate is not formed; and second ion implanting second ions each of which mass is smaller than that of each of the first ions so that a second ion impurity region is formed in the stress r
    Type: Grant
    Filed: July 26, 2005
    Date of Patent: August 7, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Kanshi Abe
  • Publication number: 20060079063
    Abstract: A method of manufacturing a semiconductor device having a semiconductor substrate that includes an active region for forming transistor elements, which includes a gate, and an element isolation region for isolating the transistor elements separately each other, which has a STI structure, the method comprises; first—ion implanting fist ions onto the surface of the semiconductor substrate in a region other than a stress region in the active region, which is located at the interface with the element isolation region, in the stress region, a potential stress is generated by forming the element isolation region and/or the difference between a material of the element isolation region and a material of the semiconductor substrate, so that a first impurity region for a source and/or a drain is formed in the active region in which the gate is not formed; and second ion implanting second ions each of which mass is smaller than that of each of the first ions so that a second ion impurity region is formed in the stress r
    Type: Application
    Filed: July 26, 2005
    Publication date: April 13, 2006
    Inventor: Kanshi Abe