Patents by Inventor Kanta Saino
Kanta Saino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10886214Abstract: A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.Type: GrantFiled: June 11, 2019Date of Patent: January 5, 2021Assignee: Micron Technology, Inc.Inventor: Kanta Saino
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Publication number: 20190295946Abstract: A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.Type: ApplicationFiled: June 11, 2019Publication date: September 26, 2019Applicant: Micron Technology, Inc.Inventor: Kanta Saino
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Patent number: 10410964Abstract: A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.Type: GrantFiled: June 12, 2018Date of Patent: September 10, 2019Assignee: Micron Technology, Inc.Inventor: Kanta Saino
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Publication number: 20180301410Abstract: A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.Type: ApplicationFiled: June 12, 2018Publication date: October 18, 2018Applicant: Micron Technology, Inc.Inventor: Kanta SAINO
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Patent number: 10074603Abstract: A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.Type: GrantFiled: February 8, 2017Date of Patent: September 11, 2018Assignee: Micron Technology, Inc.Inventor: Kanta Saino
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Publication number: 20170148731Abstract: A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.Type: ApplicationFiled: February 8, 2017Publication date: May 25, 2017Inventor: Kanta SAINO
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Patent number: 9601384Abstract: A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.Type: GrantFiled: October 5, 2015Date of Patent: March 21, 2017Assignee: Micron Technology, Inc.Inventor: Kanta Saino
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Patent number: 9461053Abstract: Disclosed embodiments relate to a semiconductor device having a plurality of unit transistors that include element isolation regions formed on a semiconductor substrate and a gate electrode formed in the shape of a frame and disposed on an active region sandwiched between the element isolation regions in such a way that the two ends of the outer periphery of the gate electrode extend onto the element isolation regions and the inner periphery thereof closes the active region. The active regions of unit transistors adjacent to one another in a first direction are electrically isolated from one another by means of the element isolation regions, and the active regions of unit transistors adjacent to one another in a second direction which intersects the first direction are linked to one another.Type: GrantFiled: February 14, 2014Date of Patent: October 4, 2016Assignee: PS4 LUXCO S.A.R.L.Inventor: Kanta Saino
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Patent number: 9263456Abstract: A semiconductor device comprises a semiconductor substrate, a first transistor including a gate insulating film and a gate electrode sequentially formed on the semiconductor substrate, a sidewall, an interlayer insulating film formed on the semiconductor substrate, and a contact plug which penetrates through the interlayer insulating film and reaches the semiconductor substrate. The sidewall is formed on a side surface of the gate electrode, and includes a first insulating film and a second insulating film formed on the first insulating film and containing a metal oxide different from the first insulating film.Type: GrantFiled: June 26, 2012Date of Patent: February 16, 2016Assignee: PS4 Luxco S.a.r.l.Inventor: Kanta Saino
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Publication number: 20160027701Abstract: A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.Type: ApplicationFiled: October 5, 2015Publication date: January 28, 2016Inventor: Kanta SAINO
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Publication number: 20160027778Abstract: One semiconductor device includes a first active region provided on a semiconductor substrate in which a transistor having a high dielectric constant gate insulating film, a gate electrode, and a diffusion layer is disposed, an element separation region that is in contact with and surrounds the first active region, and a dummy active region that is in contact with the element separation region.Type: ApplicationFiled: March 10, 2014Publication date: January 28, 2016Inventors: Yoshikazu Moriwaki, Kanta Saino
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Publication number: 20150380416Abstract: Disclosed embodiments relate to a semiconductor device having a plurality of unit transistors that include element isolation regions formed on a semiconductor substrate and a gate electrode formed in the shape of a frame and disposed on an active region sandwiched between the element isolation regions in such a way that the two ends of the outer periphery of the gate electrode extend onto the element isolation regions and the inner periphery thereof closes the active region. The active regions of unit transistors adjacent to one another in a first direction are electrically isolated from one another by means of the element isolation regions, and the active regions of unit transistors adjacent to one another in a second direction which intersects the first direction are linked to one another.Type: ApplicationFiled: February 14, 2014Publication date: December 31, 2015Inventor: Kanta Saino
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Publication number: 20150372106Abstract: A semiconductor device comprises: a memory cell region having a first transistor and a peripheral circuit region having a second transistor. The first transistor has a first source electrode and a first drain electrode, a first buried gate insulating film which is formed along an inner wall of a trench and whose relative dielectric constant is higher than a relative dielectric constant of silicon oxide, and a buried gate electrode. The second transistor has a second source electrode and a second drain electrode, a first on-substrate gate insulating film whose relative dielectric constant is higher than a relative dielectric constant of silicon oxide, and an on-substrate gate electrode. A first Hf content percentage, which is a content percentage of hafnium in the first buried gate insulating film, is different from a second Hf content percentage, which is a content percentage of hafnium in the first on-substrate gate insulating film.Type: ApplicationFiled: August 31, 2015Publication date: December 24, 2015Inventor: Kanta SAINO
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Publication number: 20150333070Abstract: The present invention provides a semiconductor device manufacturing method that reduces contact resistances in a memory cell region.Type: ApplicationFiled: December 24, 2013Publication date: November 19, 2015Inventors: Kanta Saino, Takeshi Nagai
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Patent number: 9178017Abstract: A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.Type: GrantFiled: August 4, 2014Date of Patent: November 3, 2015Assignee: Micron Technology, Inc.Inventor: Kanta Saino
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Patent number: 9153567Abstract: A semiconductor device comprises: a memory cell region having a first transistor and a peripheral circuit region having a second transistor. The first transistor has a first source electrode and a first drain electrode, a first buried gate insulating film which is formed along an inner wall of a trench and whose relative dielectric constant is higher than a relative dielectric constant of silicon oxide, and a buried gate electrode. The second transistor has a second source electrode and a second drain electrode, a first on-substrate gate insulating film whose relative dielectric constant is higher than a relative dielectric constant of silicon oxide, and an on-substrate gate electrode. A first Hf content percentage, which is a content percentage of hafnium in the first buried gate insulating film, is different from a second Hf content percentage, which is a content percentage of hafnium in the first on-substrate gate insulating film.Type: GrantFiled: May 22, 2013Date of Patent: October 6, 2015Assignee: PS4 Luxco S.a.r.l.Inventor: Kanta Saino
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Publication number: 20150064895Abstract: Provided is a method of manufacturing a semiconductor device. One exemplary embodiment involves forming a protective layer over first and second electrodes of a semiconductor device; forming a compensation film on the protective layer and between the first and second electrodes; removing the compensation film from being on the protective layer; and removing the protective layer from over the first electrode and second electrodes.Type: ApplicationFiled: November 4, 2014Publication date: March 5, 2015Inventor: Kanta SAINO
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Publication number: 20150054086Abstract: A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.Type: ApplicationFiled: August 4, 2014Publication date: February 26, 2015Inventor: Kanta SAINO
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Publication number: 20140151791Abstract: A semiconductor device comprises: a memory cell region having a first transistor and a peripheral circuit region having a second transistor. The first transistor has a first source electrode and a first drain electrode, a first buried gate insulating film which is formed along an inner wall of a trench and whose relative dielectric constant is higher than a relative dielectric constant of silicon oxide, and a buried gate electrode. The second transistor has a second source electrode and a second drain electrode, a first on-substrate gate insulating film whose relative dielectric constant is higher than a relative dielectric constant of silicon oxide, and an on-substrate gate electrode. A first Hf content percentage, which is a content percentage of hafnium in the first buried gate insulating film, is different from a second Hf content percentage, which is a content percentage of hafnium in the first on-substrate gate insulating film.Type: ApplicationFiled: May 22, 2013Publication date: June 5, 2014Applicant: Elpida Memory, Inc.Inventor: Kanta SAINO
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Patent number: 8735230Abstract: A process for manufacturing a semiconductor device consecutively includes forming a recess in the surface region of a silicon substrate, forming a gate insulation film on the surface of the recess, depositing a silicon electrode film including an oxygen-mixed layer extending parallel to the surface of the recess, injecting impurities into silicon the electrode film 17, and heat-treating the silicon electrode film to diffuse impurities.Type: GrantFiled: June 19, 2007Date of Patent: May 27, 2014Inventor: Kanta Saino