Patents by Inventor Kanta Saino

Kanta Saino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10886214
    Abstract: A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: January 5, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Kanta Saino
  • Publication number: 20190295946
    Abstract: A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.
    Type: Application
    Filed: June 11, 2019
    Publication date: September 26, 2019
    Applicant: Micron Technology, Inc.
    Inventor: Kanta Saino
  • Patent number: 10410964
    Abstract: A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: September 10, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Kanta Saino
  • Publication number: 20180301410
    Abstract: A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.
    Type: Application
    Filed: June 12, 2018
    Publication date: October 18, 2018
    Applicant: Micron Technology, Inc.
    Inventor: Kanta SAINO
  • Patent number: 10074603
    Abstract: A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: September 11, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Kanta Saino
  • Publication number: 20170148731
    Abstract: A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.
    Type: Application
    Filed: February 8, 2017
    Publication date: May 25, 2017
    Inventor: Kanta SAINO
  • Patent number: 9601384
    Abstract: A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: March 21, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Kanta Saino
  • Patent number: 9461053
    Abstract: Disclosed embodiments relate to a semiconductor device having a plurality of unit transistors that include element isolation regions formed on a semiconductor substrate and a gate electrode formed in the shape of a frame and disposed on an active region sandwiched between the element isolation regions in such a way that the two ends of the outer periphery of the gate electrode extend onto the element isolation regions and the inner periphery thereof closes the active region. The active regions of unit transistors adjacent to one another in a first direction are electrically isolated from one another by means of the element isolation regions, and the active regions of unit transistors adjacent to one another in a second direction which intersects the first direction are linked to one another.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: October 4, 2016
    Assignee: PS4 LUXCO S.A.R.L.
    Inventor: Kanta Saino
  • Patent number: 9263456
    Abstract: A semiconductor device comprises a semiconductor substrate, a first transistor including a gate insulating film and a gate electrode sequentially formed on the semiconductor substrate, a sidewall, an interlayer insulating film formed on the semiconductor substrate, and a contact plug which penetrates through the interlayer insulating film and reaches the semiconductor substrate. The sidewall is formed on a side surface of the gate electrode, and includes a first insulating film and a second insulating film formed on the first insulating film and containing a metal oxide different from the first insulating film.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: February 16, 2016
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Kanta Saino
  • Publication number: 20160027701
    Abstract: A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.
    Type: Application
    Filed: October 5, 2015
    Publication date: January 28, 2016
    Inventor: Kanta SAINO
  • Publication number: 20160027778
    Abstract: One semiconductor device includes a first active region provided on a semiconductor substrate in which a transistor having a high dielectric constant gate insulating film, a gate electrode, and a diffusion layer is disposed, an element separation region that is in contact with and surrounds the first active region, and a dummy active region that is in contact with the element separation region.
    Type: Application
    Filed: March 10, 2014
    Publication date: January 28, 2016
    Inventors: Yoshikazu Moriwaki, Kanta Saino
  • Publication number: 20150380416
    Abstract: Disclosed embodiments relate to a semiconductor device having a plurality of unit transistors that include element isolation regions formed on a semiconductor substrate and a gate electrode formed in the shape of a frame and disposed on an active region sandwiched between the element isolation regions in such a way that the two ends of the outer periphery of the gate electrode extend onto the element isolation regions and the inner periphery thereof closes the active region. The active regions of unit transistors adjacent to one another in a first direction are electrically isolated from one another by means of the element isolation regions, and the active regions of unit transistors adjacent to one another in a second direction which intersects the first direction are linked to one another.
    Type: Application
    Filed: February 14, 2014
    Publication date: December 31, 2015
    Inventor: Kanta Saino
  • Publication number: 20150372106
    Abstract: A semiconductor device comprises: a memory cell region having a first transistor and a peripheral circuit region having a second transistor. The first transistor has a first source electrode and a first drain electrode, a first buried gate insulating film which is formed along an inner wall of a trench and whose relative dielectric constant is higher than a relative dielectric constant of silicon oxide, and a buried gate electrode. The second transistor has a second source electrode and a second drain electrode, a first on-substrate gate insulating film whose relative dielectric constant is higher than a relative dielectric constant of silicon oxide, and an on-substrate gate electrode. A first Hf content percentage, which is a content percentage of hafnium in the first buried gate insulating film, is different from a second Hf content percentage, which is a content percentage of hafnium in the first on-substrate gate insulating film.
    Type: Application
    Filed: August 31, 2015
    Publication date: December 24, 2015
    Inventor: Kanta SAINO
  • Publication number: 20150333070
    Abstract: The present invention provides a semiconductor device manufacturing method that reduces contact resistances in a memory cell region.
    Type: Application
    Filed: December 24, 2013
    Publication date: November 19, 2015
    Inventors: Kanta Saino, Takeshi Nagai
  • Patent number: 9178017
    Abstract: A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: November 3, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Kanta Saino
  • Patent number: 9153567
    Abstract: A semiconductor device comprises: a memory cell region having a first transistor and a peripheral circuit region having a second transistor. The first transistor has a first source electrode and a first drain electrode, a first buried gate insulating film which is formed along an inner wall of a trench and whose relative dielectric constant is higher than a relative dielectric constant of silicon oxide, and a buried gate electrode. The second transistor has a second source electrode and a second drain electrode, a first on-substrate gate insulating film whose relative dielectric constant is higher than a relative dielectric constant of silicon oxide, and an on-substrate gate electrode. A first Hf content percentage, which is a content percentage of hafnium in the first buried gate insulating film, is different from a second Hf content percentage, which is a content percentage of hafnium in the first on-substrate gate insulating film.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: October 6, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Kanta Saino
  • Publication number: 20150064895
    Abstract: Provided is a method of manufacturing a semiconductor device. One exemplary embodiment involves forming a protective layer over first and second electrodes of a semiconductor device; forming a compensation film on the protective layer and between the first and second electrodes; removing the compensation film from being on the protective layer; and removing the protective layer from over the first electrode and second electrodes.
    Type: Application
    Filed: November 4, 2014
    Publication date: March 5, 2015
    Inventor: Kanta SAINO
  • Publication number: 20150054086
    Abstract: A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.
    Type: Application
    Filed: August 4, 2014
    Publication date: February 26, 2015
    Inventor: Kanta SAINO
  • Publication number: 20140151791
    Abstract: A semiconductor device comprises: a memory cell region having a first transistor and a peripheral circuit region having a second transistor. The first transistor has a first source electrode and a first drain electrode, a first buried gate insulating film which is formed along an inner wall of a trench and whose relative dielectric constant is higher than a relative dielectric constant of silicon oxide, and a buried gate electrode. The second transistor has a second source electrode and a second drain electrode, a first on-substrate gate insulating film whose relative dielectric constant is higher than a relative dielectric constant of silicon oxide, and an on-substrate gate electrode. A first Hf content percentage, which is a content percentage of hafnium in the first buried gate insulating film, is different from a second Hf content percentage, which is a content percentage of hafnium in the first on-substrate gate insulating film.
    Type: Application
    Filed: May 22, 2013
    Publication date: June 5, 2014
    Applicant: Elpida Memory, Inc.
    Inventor: Kanta SAINO
  • Patent number: 8735230
    Abstract: A process for manufacturing a semiconductor device consecutively includes forming a recess in the surface region of a silicon substrate, forming a gate insulation film on the surface of the recess, depositing a silicon electrode film including an oxygen-mixed layer extending parallel to the surface of the recess, injecting impurities into silicon the electrode film 17, and heat-treating the silicon electrode film to diffuse impurities.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: May 27, 2014
    Inventor: Kanta Saino